From: Suneel Garapati <suneelglinux@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v1] drivers: ahci: write upper 32 bits for clb and fis registers
Date: Wed, 6 Sep 2017 09:59:35 -0700 [thread overview]
Message-ID: <1504717175-11844-1-git-send-email-suneelglinux@gmail.com> (raw)
If 64-bit capability is supported, commandlistbase and fis base
should be split as lower32 and upper32. upper32 should be
written to PORT_(LST/FIS)_ADDR_HI.
Signed-off-by: Suneel Garapati <suneelglinux@gmail.com>
---
Changes v1:
- add macro definitions for LOWER32, UPPER32
drivers/ata/ahci.c | 14 ++++++++++++--
include/ahci.h | 1 +
2 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 5e4df19..178d9a7 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -27,6 +27,9 @@
#include <dm/device-internal.h>
#include <dm/lists.h>
+#define LOWER32(val) (u32)((u64)(val) & 0xFFFFFFFF)
+#define UPPER32(val) (u32)(((u64)(val) & 0xFFFFFFFF00000000ULL) >> 32)
+
static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
#ifndef CONFIG_DM_SCSI
@@ -607,10 +610,17 @@ static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
pp->cmd_tbl_sg =
(struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
- writel_with_flush((unsigned long)pp->cmd_slot,
+ if (uc_priv->cap & HOST_CAP_64)
+ writel_with_flush(cpu_to_le32(UPPER32(pp->cmd_slot)),
+ port_mmio + PORT_LST_ADDR_HI);
+ writel_with_flush(cpu_to_le32(LOWER32(pp->cmd_slot)),
port_mmio + PORT_LST_ADDR);
- writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
+ if (uc_priv->cap & HOST_CAP_64)
+ writel_with_flush(cpu_to_le32(UPPER32(pp->rx_fis)),
+ port_mmio + PORT_FIS_ADDR_HI);
+ writel_with_flush(cpu_to_le32(LOWER32(pp->rx_fis)),
+ port_mmio + PORT_FIS_ADDR);
#ifdef CONFIG_SUNXI_AHCI
sunxi_dma_init(port_mmio);
diff --git a/include/ahci.h b/include/ahci.h
index 33171b7..80e7f13 100644
--- a/include/ahci.h
+++ b/include/ahci.h
@@ -40,6 +40,7 @@
#define HOST_RESET (1 << 0) /* reset controller; self-clear */
#define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
#define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
+#define HOST_CAP_64 (1 << 31) /* 64bit addressing capability */
/* Registers for each SATA port */
#define PORT_LST_ADDR 0x00 /* command list DMA addr */
--
2.7.4
next reply other threads:[~2017-09-06 16:59 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-06 16:59 Suneel Garapati [this message]
2017-09-11 6:17 ` [U-Boot] [PATCH v1] drivers: ahci: write upper 32 bits for clb and fis registers Simon Glass
2017-09-13 13:23 ` [U-Boot] [U-Boot, " Tom Rini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1504717175-11844-1-git-send-email-suneelglinux@gmail.com \
--to=suneelglinux@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox