From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10
Date: Wed, 27 Sep 2017 04:55:14 +0000 [thread overview]
Message-ID: <1506488114.3589.12.camel@intel.com> (raw)
In-Reply-To: <79e2d85b-09ec-fa59-ce95-955dddf9adbe@denx.de>
On Sel, 2017-09-26 at 12:35 +0200, Marek Vasut wrote:
> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> >
> > On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
> > >
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > Add DDR driver suppport for Arria 10.
> > > >
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > > arch/arm/mach-socfpga/include/mach/sdram.h | 2 +
> > > > arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> > > > drivers/ddr/altera/sdram_arria10.c | 735
> > > > +++++++++++++++++++++
> > > > 3 files changed, 839 insertions(+), 1 deletion(-)
> > > > create mode 100644 drivers/ddr/altera/sdram_arria10.c
> > > >
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index 4a9754e..b833fc2 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -10,6 +10,8 @@
> > > >
> > > > #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > > #include <asm/arch/sdram_gen5.h>
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#include <asm/arch/sdram_arria10.h>
> > > > #endif
> > > >
> > > > #endif
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > index 1d7b7c1..7af9431 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > @@ -1,5 +1,5 @@
> > > > /*
> > > > - * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
> > > > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > > *
> > > > * SPDX-License-Identifier: GPL-2.0
> > > > */
> > > > @@ -8,6 +8,7 @@
> > > > #define _SOCFPGA_SDRAM_ARRIA10_H_
> > > >
> > > > #ifndef __ASSEMBLY__
> > > > +int ddr_calibration_sequence(void);
> > > >
> > > > struct socfpga_ecc_hmc {
> > > > u32 ip_rev_id;
> > > > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
> > > > u32 niosreserve1;
> > > > u32 niosreserve2;
> > > > };
> > > > +
> > > > +union dramaddrw_reg {
> > > > + struct {
> > > > + u32 cfg_col_addr_width:5;
> > > > + u32 cfg_row_addr_width:5;
> > > > + u32 cfg_bank_addr_width:4;
> > > > + u32 cfg_bank_group_addr_width:2;
> > > > + u32 cfg_cs_addr_width:3;
> > > > + u32 reserved:13;
> > > > + };
> > > Use regular macros for bitfields, not this crap.
> > >
> > Why regular macros is prefered? Above implementation improve
> > readability, simplify the implementation and saving memory.
> Because that's how U-Boot does it (and the above afair breaks on
> different endianness).
>
Okay.
> >
> > >
> > > >
> > > >
> > > > + u32 word;
> > > > +};
> > > > +
> > > > +union ctrlcfg0_reg {
> > > > + struct {
> > > > + u32 cfg_mem_type:4;
> > > > + u32 cfg_dimm_type:3;
> > > > + u32 cfg_ac_pos:2;
> > > > + u32 cfg_ctrl_burst_len:5;
> > > > + u32 reserved:18; /* Other fields unused */
> > > > + };
> > > > + u32 word;
> > > > +};
> > > [...]
> [...]
>
next prev parent reply other threads:[~2017-09-27 4:55 UTC|newest]
Thread overview: 88+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-25 8:39 [U-Boot] [PATCH v2 00/19] Add FPGA, SDRAM, SPL loads U-boot & booting to console tien.fong.chee at intel.com
2017-09-25 8:39 ` [U-Boot] [PATCH v2 01/19] ARM: socfpga: add bindings doc for arria10 fpga manager tien.fong.chee at intel.com
2017-09-25 8:59 ` Marek Vasut
2017-09-25 8:39 ` [U-Boot] [PATCH v2 02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager tien.fong.chee at intel.com
2017-09-25 9:00 ` Marek Vasut
2017-09-26 8:54 ` Chee, Tien Fong
2017-09-26 10:30 ` Marek Vasut
2017-09-27 3:12 ` Chee, Tien Fong
2017-09-27 8:29 ` Marek Vasut
2017-09-28 2:49 ` Chee, Tien Fong
2017-09-25 9:01 ` Marek Vasut
2017-09-26 8:32 ` Chee, Tien Fong
2017-09-25 8:39 ` [U-Boot] [PATCH v2 03/19] dts: Add FPGA bitstream properties to Arria 10 DTS tien.fong.chee at intel.com
2017-09-25 8:40 ` [U-Boot] [PATCH v2 04/19] arm: socfpga: Add Arria 10 SoCFPGA programming interface tien.fong.chee at intel.com
2017-09-25 9:03 ` Marek Vasut
2017-09-29 7:42 ` Chee, Tien Fong
2017-09-25 8:40 ` [U-Boot] [PATCH v2 05/19] arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes tien.fong.chee at intel.com
2017-09-25 9:08 ` Marek Vasut
2017-09-25 8:40 ` [U-Boot] [PATCH v2 06/19] dts: Enable fpga-mgr node build for Arria 10 SPL tien.fong.chee at intel.com
2017-09-25 8:40 ` [U-Boot] [PATCH v2 07/19] fdt: Add compatible strings for Arria 10 tien.fong.chee at intel.com
2017-09-25 9:08 ` Marek Vasut
2017-12-10 19:34 ` Simon Glass
2017-09-25 8:40 ` [U-Boot] [PATCH v2 08/19] fs: Enable generic filesystems interface support in SPL tien.fong.chee at intel.com
2017-09-25 9:09 ` Marek Vasut
2017-10-09 4:47 ` Simon Glass
2017-09-25 8:40 ` [U-Boot] [PATCH v2 09/19] arm: socfpga: Add drivers for programing FPGA from flash tien.fong.chee at intel.com
2017-09-25 9:14 ` Marek Vasut
2017-09-26 8:30 ` Chee, Tien Fong
2017-09-26 10:32 ` Marek Vasut
2017-09-27 6:05 ` Chee, Tien Fong
2017-09-27 8:30 ` Marek Vasut
2017-09-28 2:45 ` Chee, Tien Fong
2017-09-26 9:52 ` Chee, Tien Fong
2017-09-26 10:39 ` Marek Vasut
2017-09-27 9:13 ` Chee, Tien Fong
2017-09-27 9:23 ` Marek Vasut
2017-09-28 15:14 ` Chee, Tien Fong
2017-09-28 15:18 ` Marek Vasut
2017-10-09 4:47 ` Simon Glass
2017-09-25 8:40 ` [U-Boot] [PATCH v2 10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name tien.fong.chee at intel.com
2017-09-25 9:15 ` Marek Vasut
2017-09-26 8:23 ` Chee, Tien Fong
2017-09-26 10:33 ` Marek Vasut
2017-09-27 5:06 ` Chee, Tien Fong
2017-09-25 8:40 ` [U-Boot] [PATCH v2 11/19] arm: socfpga: Add DRAM bank size initialization function tien.fong.chee at intel.com
2017-09-25 9:15 ` Marek Vasut
2017-09-26 8:20 ` Chee, Tien Fong
2017-09-26 10:33 ` Marek Vasut
2017-10-02 10:01 ` Chee, Tien Fong
2017-10-02 10:04 ` Marek Vasut
2017-10-02 10:06 ` Chee, Tien Fong
2017-10-03 3:30 ` Ley Foon Tan
2017-09-25 8:40 ` [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for Arria 10 tien.fong.chee at intel.com
2017-09-25 9:19 ` Marek Vasut
2017-09-26 8:20 ` Chee, Tien Fong
2017-09-26 10:35 ` Marek Vasut
2017-09-27 4:55 ` Chee, Tien Fong [this message]
2017-09-25 8:40 ` [U-Boot] [PATCH v2 13/19] configs: Add DDR Kconfig support " tien.fong.chee at intel.com
2017-09-25 8:40 ` [U-Boot] [PATCH v2 14/19] arm: socfpga: Enable build for DDR " tien.fong.chee at intel.com
2017-09-25 9:20 ` Marek Vasut
2017-09-26 5:06 ` Chee, Tien Fong
2017-09-25 8:40 ` [U-Boot] [PATCH v2 15/19] arm: socfpga: Add support to memory allocation in SPL tien.fong.chee at intel.com
2017-09-25 9:21 ` Marek Vasut
2017-09-26 5:06 ` Chee, Tien Fong
2017-09-26 10:37 ` Marek Vasut
2017-09-27 5:43 ` Chee, Tien Fong
2017-09-27 8:32 ` Marek Vasut
2017-09-28 2:48 ` Chee, Tien Fong
2017-09-25 8:40 ` [U-Boot] [PATCH v2 16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 tien.fong.chee at intel.com
2017-09-25 9:23 ` Marek Vasut
2017-09-26 4:42 ` Chee, Tien Fong
2017-09-26 10:37 ` Marek Vasut
2017-09-27 3:30 ` Chee, Tien Fong
2017-09-27 8:33 ` Marek Vasut
2017-09-28 2:46 ` Chee, Tien Fong
2017-09-25 8:40 ` [U-Boot] [PATCH v2 17/19] arm: socfpga: Adding clock frequency info for U-boot tien.fong.chee at intel.com
2017-09-25 9:23 ` Marek Vasut
2017-09-26 4:32 ` Chee, Tien Fong
2017-09-27 3:24 ` Chee, Tien Fong
2017-10-02 10:04 ` Chee, Tien Fong
2017-10-02 10:10 ` Marek Vasut
2017-10-02 10:25 ` Chee, Tien Fong
2017-09-25 8:40 ` [U-Boot] [PATCH v2 18/19] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot tien.fong.chee at intel.com
2017-09-25 8:40 ` [U-Boot] [PATCH v2 19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot tien.fong.chee at intel.com
2017-09-25 9:24 ` Marek Vasut
2017-09-26 4:31 ` Chee, Tien Fong
2017-09-26 10:38 ` Marek Vasut
2017-09-27 3:14 ` Chee, Tien Fong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1506488114.3589.12.camel@intel.com \
--to=tien.fong.chee@intel.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox