From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chee, Tien Fong <tien.fong.chee@intel.com>
Date: Wed, 27 Sep 2017 04:55:14 +0000
Subject: [U-Boot] [PATCH v2 12/19] arm: socfpga: Add DDR driver for
	Arria 10
In-Reply-To: <79e2d85b-09ec-fa59-ce95-955dddf9adbe@denx.de>
References: <1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>
 <1506328815-23733-13-git-send-email-tien.fong.chee@intel.com>
 <34f4649f-e202-3a63-4aff-e2c14d5dff82@denx.de>
 <1506414031.27760.20.camel@intel.com>
 <79e2d85b-09ec-fa59-ce95-955dddf9adbe@denx.de>
Message-ID: <1506488114.3589.12.camel@intel.com>
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On Sel, 2017-09-26 at 12:35 +0200, Marek Vasut wrote:
> On 09/26/2017 10:20 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-25 at 11:19 +0200, Marek Vasut wrote:
> > > 
> > > On 09/25/2017 10:40 AM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Add DDR driver suppport for Arria 10.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > ---
> > > >  arch/arm/mach-socfpga/include/mach/sdram.h         |   2 +
> > > >  arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 ++-
> > > >  drivers/ddr/altera/sdram_arria10.c                 | 735
> > > > +++++++++++++++++++++
> > > >  3 files changed, 839 insertions(+), 1 deletion(-)
> > > >  create mode 100644 drivers/ddr/altera/sdram_arria10.c
> > > > 
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > index 4a9754e..b833fc2 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram.h
> > > > @@ -10,6 +10,8 @@
> > > >  
> > > >  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > > >  #include <asm/arch/sdram_gen5.h>
> > > > +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > > > +#include <asm/arch/sdram_arria10.h>
> > > >  #endif
> > > >  
> > > >  #endif
> > > > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > index 1d7b7c1..7af9431 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/sdram_arria10.h
> > > > @@ -1,5 +1,5 @@
> > > >  /*
> > > > - * Copyright (C) 2015-2017 Intel Corporation <www.intel.com>
> > > > + * Copyright (C) 2017 Intel Corporation <www.intel.com>
> > > >   *
> > > >   * SPDX-License-Identifier:	GPL-2.0
> > > >   */
> > > > @@ -8,6 +8,7 @@
> > > >  #define _SOCFPGA_SDRAM_ARRIA10_H_
> > > >  
> > > >  #ifndef __ASSEMBLY__
> > > > +int ddr_calibration_sequence(void);
> > > >  
> > > >  struct socfpga_ecc_hmc {
> > > >  	u32 ip_rev_id;
> > > > @@ -204,6 +205,106 @@ struct socfpga_io48_mmr {
> > > >  	u32 niosreserve1;
> > > >  	u32 niosreserve2;
> > > >  };
> > > > +
> > > > +union dramaddrw_reg {
> > > > +	struct {
> > > > +		u32 cfg_col_addr_width:5;
> > > > +		u32 cfg_row_addr_width:5;
> > > > +		u32 cfg_bank_addr_width:4;
> > > > +		u32 cfg_bank_group_addr_width:2;
> > > > +		u32 cfg_cs_addr_width:3;
> > > > +		u32 reserved:13;
> > > > +	};
> > > Use regular macros for bitfields, not this crap.
> > > 
> > Why regular macros is prefered? Above implementation improve
> > readability, simplify the implementation and saving memory.
> Because that's how U-Boot does it (and the above afair breaks on
> different endianness).
> 
Okay.
> > 
> > > 
> > > > 
> > > > 
> > > > +	u32 word;
> > > > +};
> > > > +
> > > > +union ctrlcfg0_reg {
> > > > +	struct {
> > > > +		u32 cfg_mem_type:4;
> > > > +		u32 cfg_dimm_type:3;
> > > > +		u32 cfg_ac_pos:2;
> > > > +		u32 cfg_ctrl_burst_len:5;
> > > > +		u32 reserved:18;  /* Other fields unused */
> > > > +	};
> > > > +	u32 word;
> > > > +};
> > > [...]
> [...]
>