From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Date: Tue, 03 Oct 2017 12:08:59 +0300 Subject: [U-Boot] [PATCH] dwc: ep0: Allocate and flush dwc->ep0_trb in a cache aligned manner In-Reply-To: <60a68e65-e6c4-3371-90a5-3cc782e99e3e@ti.com> References: <1505819741-29843-1-git-send-email-faiz_abbas@ti.com> <60a68e65-e6c4-3371-90a5-3cc782e99e3e@ti.com> Message-ID: <1507021739.16112.227.camel@linux.intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Tue, 2017-10-03 at 13:05 +0530, Faiz Abbas wrote: > Hi, > > On Tuesday 19 September 2017 04:45 PM, Faiz Abbas wrote: > > A flush of the cache is required before any DMA access can take > > place. > > The minimum size that can be flushed from the cache is one cache > > line > > size. Therefore, any buffer allocated for DMA should be in multiples > > of cache line size. > > > > Thus, allocate memory for ep0_trb in multiples of cache line size. > > > > Also, when local variable trb is assigned to dwc->ep0_trb[1] and > > used > > to flush cache, it leads to cache misaligned messages as only the > > base > > address dwc->ep0_trb is cache aligned. > > > > Therefore, flush cache using ep0_trb_addr which is always cache > > aligned. > > > > Signed-off-by: Faiz Abbas > > Gentle ping. Can you resend with Felipe Balbi included? And I'm not sure Vincent is anyhow related to this anymore (or even works with us). -- Andy Shevchenko Intel Finland Oy