[U-Boot] [PATCH] mx7dsabresd: Remove CONFIG_DM_MMC to avoid regression

Fabio Estevam
2017-10-11T14:23:40Z

Since U-Boot 2017.09 it is no longer possible to boot a kernel from SD
card:

U-Boot 2017.11-rc1-00149-g38c8107-dirty (Oct 11 2017 - 09:55:22 -0300)

CPU: Freescale i.MX7D rev1.2 1000 MHz (running at 792 MHz)
CPU: Commercial temperature grade (0C to 95C) at 35C
Reset cause: POR
Model: Freescale i.MX7 SabreSD Board
Board: i.MX7D SABRESD in non-secure mode
DRAM: 1 GiB
MMC: MMC/SD: Reset never completed.

MMC Device 0 not found
*** Warning - No MMC card found, using default environment

While a proper fix is not available, remove CONFIG_DM_MMC and register
the USDHC1 port in the old way, so that this board can boot a kernel
again.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
board/freescale/mx7dsabresd/mx7dsabresd.c | 42 +++++++++++++++++++++++++++++++
configs/mx7dsabresd_defconfig | 1 -
2 files changed, 42 insertions(+), 1 deletion(-)

diff --git a/board/freescale/mx7dsabresd/mx7dsabresd.c b/board/freescale/mx7dsabresd/mx7dsabresd.c
index 5819b18..12f7c58 100644
--- a/board/freescale/mx7dsabresd/mx7dsabresd.c
+++ b/board/freescale/mx7dsabresd/mx7dsabresd.c
@@ -29,6 +29,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)

+#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
+ PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
+
#define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
#define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)

@@ -191,6 +194,18 @@ static iomux_v3_cfg_t const fec1_pads[] = {
MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
};

+static iomux_v3_cfg_t const usdhc1_pads[] = {
+ MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+};
+
static void setup_iomux_fec(void)
{
imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
@@ -218,6 +233,33 @@ int mmc_map_to_kernel_blk(int dev_no)
return dev_no;
}

+#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0)
+#define USDHC1_PWR_GPIO IMX_GPIO_NR(5, 2)
+
+static struct fsl_esdhc_cfg usdhc_cfg[3] = {
+ {USDHC1_BASE_ADDR, 0, 4},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ return !gpio_get_value(USDHC1_CD_GPIO);
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
+ gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
+ gpio_direction_input(USDHC1_CD_GPIO);
+ gpio_request(USDHC1_PWR_GPIO, "usdhc1_pwr");
+ gpio_direction_output(USDHC1_PWR_GPIO, 0);
+ udelay(500);
+ gpio_direction_output(USDHC1_PWR_GPIO, 1);
+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+
+ return 0;
+}
+
#ifdef CONFIG_FEC_MXC
int board_eth_init(bd_t *bis)
{
diff --git a/configs/mx7dsabresd_defconfig b/configs/mx7dsabresd_defconfig
index 26250fd..9e07a94 100644
--- a/configs/mx7dsabresd_defconfig
+++ b/configs/mx7dsabresd_defconfig
@@ -44,7 +44,6 @@ CONFIG_DFU_RAM=y
CONFIG_DM_GPIO=y
CONFIG_DM_74X164=y
CONFIG_DM_I2C=y
-CONFIG_DM_MMC=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_EON=y
CONFIG_PHYLIB=y
--
2.7.4