[U-Boot] [PATCH v3 03/20] arm: socfpga: Add Arria 10 SoCFPGA programming interface

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Isn, 2017-10-16 at 07:39 -0500, Dinh Nguyen wrote:
> Please run get_maintainer on this patch. I think you need to include
> a
> few more people.
> 
Okay.
> On 10/13/2017 03:08 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Add code necessary into the FPGA driver framework in U-Boot
> > so it can be used via the 'fpga' command for programing Arria 10
> > SoCFPGA.
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  cmd/fpga.c            |  2 +-
> >  drivers/fpga/altera.c | 40 ++++++++++++++++++++++++++++++++-------
> > -
> >  drivers/fpga/fpga.c   |  8 ++++++++
> >  include/fpga.h        |  2 ++
> >  4 files changed, 43 insertions(+), 9 deletions(-)
> > 
> > diff --git a/cmd/fpga.c b/cmd/fpga.c
> > index ac6f504..3cb0bcd 100644
> > --- a/cmd/fpga.c
> > +++ b/cmd/fpga.c
> > @@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,
> >  	   "(Xilinx only)\n"
> >  #endif
> >  #if defined(CONFIG_CMD_FPGA_LOADFS)
> > -	   "Load device from filesystem (FAT by default) (Xilinx
> > only)\n"
> > +	   "Load device from filesystem (FAT by default)\n
> >  	   "  loadfs [dev] [address] [image size] [blocksize]
> > <interface>\n"
> >  	   "        [<dev[:part]>] <filename>\n"
> >  #endif
> > diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
> > index 135a357..a03e835 100644
> > --- a/drivers/fpga/altera.c
> > +++ b/drivers/fpga/altera.c
> > @@ -23,25 +23,31 @@ static const struct altera_fpga {
> >  	enum altera_family	family;
> >  	const char		*name;
> >  	int			(*load)(Altera_desc *, const
> > void *, size_t);
> > +	int (*loadfs)(Altera_desc *, const void *, size_t,
> > fpga_fs_info *);
> >  	int			(*dump)(Altera_desc *, const
> > void *, size_t);
> >  	int			(*info)(Altera_desc *);
> >  } altera_fpga[] = {
> >  #if defined(CONFIG_FPGA_ACEX1K)
> > -	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump,
> > ACEX1K_info },
> > -	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, ACEX1K_dump,
> > ACEX1K_info },
> > +	{ Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
> > +	 ACEX1K_info },
> > +	{ Altera_CYC2,   "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
> > +	 ACEX1K_info },
> >  #elif defined(CONFIG_FPGA_CYCLON2)
> > -	{ Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump,
> > CYC2_info },
> > -	{ Altera_CYC2,   "CycloneII", CYC2_load, CYC2_dump,
> > CYC2_info },
> > +	{ Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump,
> > CYC2_info },
> > +	{ Altera_CYC2,   "CycloneII", CYC2_load, NULL, CYC2_dump,
> > CYC2_info },
> >  #endif
> >  #if defined(CONFIG_FPGA_STRATIX_II)
> > -	{ Altera_StratixII, "StratixII", StratixII_load,
> > +	{ Altera_StratixII, "StratixII", StratixII_load, NULL,
> >  	  StratixII_dump, StratixII_info },
> >  #endif
> >  #if defined(CONFIG_FPGA_STRATIX_V)
> > -	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL
> > },
> > +	{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL,
> > NULL },
> What is the purpose of the above 3 changes if this patch is for
> Arria10?
> 
I only added new lines related to fpga loadfs. I believe above 3
changes were due to location change when new lines were appended on top
of them. 
> Dinh