From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chee, Tien Fong <tien.fong.chee@intel.com>
Date: Mon, 23 Oct 2017 06:49:55 +0000
Subject: [U-Boot] [PATCH v3 07/20] arm: socfpga: Fix with the correct
 polling status bit
In-Reply-To: <3290f265-13a5-25d2-9d5c-e9a135301958@kernel.org>
References: <1507882137-27841-1-git-send-email-tien.fong.chee@intel.com>
 <1507882137-27841-8-git-send-email-tien.fong.chee@intel.com>
 <3290f265-13a5-25d2-9d5c-e9a135301958@kernel.org>
Message-ID: <1508741394.3650.14.camel@intel.com>
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To: u-boot@lists.denx.de

On Isn, 2017-10-16 at 10:29 -0500, Dinh Nguyen wrote:
> 
> On 10/13/2017 03:08 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Commit 2baa997240d ("arm: socfpga: Add FPGA driver support for
> > Arria 10")
> > Polling the wrong status bit. Fix with correct polling status bit.
> This message doesn't reflect what the patch is doing. The patch is
> checking for the bit be set or cleared, not the status bit.
> 
This is not status register bit. This is just for false or true status.
I can improve the comment.

> Dinh
> > 
> > 
> > Fixes: 2baa997240d ("arm: socfpga: Add FPGA driver support for
> > Arria 10")
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> >  drivers/fpga/socfpga_arria10.c | 7 ++++---
> >  1 file changed, 4 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index 5c1a68a..e076bda 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -112,13 +112,14 @@ static int
> > wait_for_nconfig_pin_and_nstatus_pin(void)
> >  	unsigned long mask =
> > ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
> >  				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU
> > S_PIN_SET_MSK;
> >  
> > -	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
> > until de-asserted,
> > -	 * timeout at 1000ms
> > +	/*
> > +	 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop
> > until
> > +	 * de-asserted, timeout at 1000ms
> >  	 */
> >  	return wait_for_bit(__func__,
> >  			    &fpga_manager_base->imgcfg_stat,
> >  			    mask,
> > -			    false, FPGA_TIMEOUT_MSEC, false);
> > +			    true, FPGA_TIMEOUT_MSEC, false);
> >  }
> >  
> >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> >