From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 17/20] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot
Date: Mon, 23 Oct 2017 08:13:51 +0000 [thread overview]
Message-ID: <1508746430.3650.47.camel@intel.com> (raw)
In-Reply-To: <b0ee6d25-2478-cf85-629b-ab5c2f29fa31@kernel.org>
On Jum, 2017-10-20 at 09:33 -0500, Dinh Nguyen wrote:
>
> On 10/13/2017 03:08 AM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > SoC FPGA info is required in both SPL and U-boot.
> s/SoC FPGA/SocFPGA to be consistent.
>
> s/U-boot/U-Boot
>
Okay.
> >
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> > arch/arm/mach-socfpga/board.c | 3 +++
> > arch/arm/mach-socfpga/misc_arria10.c | 5 -----
> > arch/arm/mach-socfpga/spl.c | 6 ++++++
> > 3 files changed, 9 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-
> > socfpga/board.c
> > index 9a96f52..7beb347 100644
> > --- a/arch/arm/mach-socfpga/board.c
> > +++ b/arch/arm/mach-socfpga/board.c
> > @@ -32,6 +32,9 @@ int board_init(void)
> > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > /* configuring the clock based on handoff */
> > cm_basic_init(gd->fdt_blob);
> > +
> > + /* Add device descriptor to FPGA device table */
> > + socfpga_fpga_add();
> > #endif
> >
> > return 0;
> > diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-
> > socfpga/misc_arria10.c
> > index 9d751f6..8760ac9 100644
> > --- a/arch/arm/mach-socfpga/misc_arria10.c
> > +++ b/arch/arm/mach-socfpga/misc_arria10.c
> > @@ -94,11 +94,6 @@ int arch_early_init_r(void)
> > /* assert reset to all except L4WD0 and L4TIMER0 */
> > socfpga_per_reset_all();
> >
> > - /* configuring the clock based on handoff */
> > - /* TODO: Add call to cm_basic_init() */
> > -
> > - /* Add device descriptor to FPGA device table */
> > - socfpga_fpga_add();
> Why remove it from here?
>
Initially, this is only created for SPL. Until U-Boot enable
development phase, i realized this also required by U-boot. So i
duplicated socfpga_fpga_add in both SPL(spl.c - below) and U-
Boot(board.c - above).
> >
> > return 0;
> > }
> > #else
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index 71bae82..aba116d 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> > @@ -15,6 +15,7 @@
> > #include <asm/arch/system_manager.h>
> > #include <asm/arch/freeze_controller.h>
> > #include <asm/arch/clock_manager.h>
> > +#include <asm/arch/misc.h>
> > #include <asm/arch/scan_manager.h>
> > #include <asm/arch/sdram.h>
> > #include <asm/arch/scu.h>
> > @@ -208,6 +209,11 @@ void spl_board_init(void)
> >
> > /* enable console uart printing */
> > preloader_console_init();
> > +
> > + WATCHDOG_RESET();
> > +
> > + /* Add device descriptor to FPGA device table */
> > + socfpga_fpga_add();
> And add here?
>
Refer to my comment above.
> Dinh
next prev parent reply other threads:[~2017-10-23 8:13 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-13 8:08 [U-Boot] [PATCH v3 00/20] Add FPGA, SDRAM, SPL loadfs U-boot & booting to console tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 02/20] dts: Add FPGA bitstream properties to Arria 10 DTS tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 03/20] arm: socfpga: Add Arria 10 SoCFPGA programming interface tien.fong.chee at intel.com
2017-10-16 12:39 ` Dinh Nguyen
2017-10-23 6:46 ` Chee, Tien Fong
2017-10-23 7:04 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 04/20] dts: Enable fpga-mgr node build for Arria 10 SPL tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 05/20] fs: Enable generic filesystems interface support in SPL tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 06/20] common: Generic firmware loader for file system tien.fong.chee at intel.com
2017-10-16 14:08 ` Dinh Nguyen
2017-10-16 14:41 ` Marek Vasut
2017-10-23 6:37 ` Chee, Tien Fong
2017-10-26 12:51 ` Lukasz Majewski
2017-10-27 9:23 ` Chee, Tien Fong
2017-10-27 10:35 ` Lukasz Majewski
2017-10-28 11:32 ` Marek Vasut
2017-10-28 21:43 ` Lukasz Majewski
2017-10-29 9:35 ` Marek Vasut
2017-10-29 22:57 ` Lukasz Majewski
2017-10-29 22:59 ` Marek Vasut
2017-10-13 8:08 ` [U-Boot] [PATCH v3 07/20] arm: socfpga: Fix with the correct polling status bit tien.fong.chee at intel.com
2017-10-16 15:29 ` Dinh Nguyen
2017-10-23 6:49 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 08/20] arm: socfpga: Add drivers for programing FPGA from flash tien.fong.chee at intel.com
2017-10-16 15:33 ` Dinh Nguyen
2017-10-24 5:52 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 09/20] arm: socfpga: Rename the gen5 sdram driver to more specific name tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 10/20] arm: socfpga: Add DRAM bank size initialization function tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 11/20] arm: socfpga: Add DDR driver for Arria 10 tien.fong.chee at intel.com
2017-10-17 3:08 ` Dinh Nguyen
2017-10-23 7:45 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 12/20] configs: Add DDR Kconfig support " tien.fong.chee at intel.com
2017-10-17 3:21 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 13/20] arm: socfpga: Enable SPL memory allocation tien.fong.chee at intel.com
2017-10-17 3:44 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 14/20] arm: socfpga: Improve comments for Intel SoCFPGA program header tien.fong.chee at intel.com
2017-10-20 14:18 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 15/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 tien.fong.chee at intel.com
2017-10-20 14:19 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 16/20] arm: socfpga: Adding clock frequency info for U-boot tien.fong.chee at intel.com
2017-10-20 14:29 ` Dinh Nguyen
2017-10-23 8:02 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 17/20] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot tien.fong.chee at intel.com
2017-10-20 14:33 ` Dinh Nguyen
2017-10-23 8:13 ` Chee, Tien Fong [this message]
2017-10-13 8:08 ` [U-Boot] [PATCH v3 18/20] arm: socfpga: Enable function visible to other file tien.fong.chee at intel.com
2017-10-20 14:39 ` Dinh Nguyen
2017-10-23 8:19 ` Chee, Tien Fong
2017-10-23 14:24 ` Dinh Nguyen
2017-10-24 5:11 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working tien.fong.chee at intel.com
2017-10-20 15:11 ` Dinh Nguyen
2017-10-24 5:34 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 20/20] arm: socfpga: Enable SPL booting U-boot tien.fong.chee at intel.com
2017-10-20 15:21 ` Dinh Nguyen
2017-10-24 5:37 ` Chee, Tien Fong
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