From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working
Date: Tue, 24 Oct 2017 05:34:46 +0000 [thread overview]
Message-ID: <1508823284.2221.4.camel@intel.com> (raw)
In-Reply-To: <9833762a-4278-8cfc-177f-aa0ac41659f7@kernel.org>
On Jum, 2017-10-20 at 10:11 -0500, Dinh Nguyen wrote:
> Please update your commit header.
>
> On 10/13/2017 03:08 AM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > SPL configures DDR by programming peripheral raw binary file
> > and calibrating DDR.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > ---
> > arch/arm/mach-socfpga/spl.c | 56
> > +++++++++++++++++++++++++++++++++++++++++++++
> > 1 file changed, 56 insertions(+)
> >
> > diff --git a/arch/arm/mach-socfpga/spl.c b/arch/arm/mach-
> > socfpga/spl.c
> > index aba116d..6c9bf81 100644
> > --- a/arch/arm/mach-socfpga/spl.c
> > +++ b/arch/arm/mach-socfpga/spl.c
> > @@ -15,6 +15,7 @@
> > #include <asm/arch/system_manager.h>
> > #include <asm/arch/freeze_controller.h>
> > #include <asm/arch/clock_manager.h>
> > +#include <asm/arch/fpga_manager.h>
> > #include <asm/arch/misc.h>
> > #include <asm/arch/scan_manager.h>
> > #include <asm/arch/sdram.h>
> > @@ -22,6 +23,10 @@
> > #include <asm/arch/nic301.h>
> > #include <asm/sections.h>
> > #include <fdtdec.h>
> > +#include <fat.h>
> > +#include <fs.h>
> > +#include <linux/ctype.h>
> > +#include <mmc.h>
> > #include <watchdog.h>
> > #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > #include <asm/arch/pinmux.h>
> > @@ -29,6 +34,9 @@
> >
> > DECLARE_GLOBAL_DATA_PTR;
> >
> > +#define BSIZE 4096
> > +#define PERIPH_RBF 0
> > +
> > #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> > static struct pl310_regs *const pl310 =
> > (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> > @@ -197,6 +205,12 @@ void board_init_f(ulong dummy)
> > #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> > void spl_board_init(void)
> > {
> > + int rval = 0;
> > + int len = 0;
> > + u32 buffer[BSIZE] __aligned(ARCH_DMA_MINALIGN);
> > + struct spl_boot_device bootdev;
> > + fpga_fs_info fpga_fsinfo;
> > +
> > /* configuring the clock based on handoff */
> > cm_basic_init(gd->fdt_blob);
> > WATCHDOG_RESET();
> > @@ -214,6 +228,48 @@ void spl_board_init(void)
> >
> > /* Add device descriptor to FPGA device table */
> > socfpga_fpga_add();
> > +
> > + bootdev.boot_device = spl_boot_device();
> > +
> > + if (BOOT_DEVICE_MMC1 == bootdev.boot_device) {
> > + struct mmc *mmc = NULL;
> > + int err = 0;
> > +
> > + spl_mmc_find_device(&mmc, bootdev.boot_device);
> > +
> > + err = mmc_init(mmc);
> > +
> > + if (err) {
> > +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
> > + printf("spl: mmc init failed with error:
> > %d\n", err);
> You should use puts instead of printf. But this case use error()? Why
> do
> you need to wrap this around CONFIG_SPL_LIBCOMMON_SUPPORT?
>
I copied this block of code from /common/spl_mmc.c, so i keep
everything intact. But, i tried to track back the reason of wrapping
around with CONFIG_SPL_LIBCOMMON_SUPPORT, this is what i found "If we
don't have CONFIG_SPL_LIBCOMMON_SUPPORT defined then stdio
functions are unavailable & calling them will cause a link failure."
https://lists.denx.de/pipermail/u-boot/2013-September/161969.html
> >
> > +#endif
> > + return;
> > + }
> > +
> > + fpga_fsinfo.interface = "mmc";
> > + fpga_fsinfo.fstype = FS_TYPE_FAT;
> > + }
> > +
> > + fpga_fsinfo.dev_part = (char *)get_cff_devpart(gd-
> > >fdt_blob,
> > + &len);
> > +
> > + fpga_fsinfo.filename = (char *)get_cff_filename(gd-
> > >fdt_blob,
> > + &len,
> > + PERIPH_RB
> > F);
> > +
> > + /* Program peripheral RBF */
> > + if (fpga_fsinfo.filename)
> > + rval = fpga_fsload(0, buffer, BSIZE,
> > &fpga_fsinfo);
> > + else {
> > + printf("Failed to find peripheral RBF file from
> > DTS\n");
> Use error()?
>
Okay.
> Dinh
next prev parent reply other threads:[~2017-10-24 5:34 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-13 8:08 [U-Boot] [PATCH v3 00/20] Add FPGA, SDRAM, SPL loadfs U-boot & booting to console tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 01/20] ARM: socfpga: Description on FPGA RBF properties at Arria 10 FPGA manager tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 02/20] dts: Add FPGA bitstream properties to Arria 10 DTS tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 03/20] arm: socfpga: Add Arria 10 SoCFPGA programming interface tien.fong.chee at intel.com
2017-10-16 12:39 ` Dinh Nguyen
2017-10-23 6:46 ` Chee, Tien Fong
2017-10-23 7:04 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 04/20] dts: Enable fpga-mgr node build for Arria 10 SPL tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 05/20] fs: Enable generic filesystems interface support in SPL tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 06/20] common: Generic firmware loader for file system tien.fong.chee at intel.com
2017-10-16 14:08 ` Dinh Nguyen
2017-10-16 14:41 ` Marek Vasut
2017-10-23 6:37 ` Chee, Tien Fong
2017-10-26 12:51 ` Lukasz Majewski
2017-10-27 9:23 ` Chee, Tien Fong
2017-10-27 10:35 ` Lukasz Majewski
2017-10-28 11:32 ` Marek Vasut
2017-10-28 21:43 ` Lukasz Majewski
2017-10-29 9:35 ` Marek Vasut
2017-10-29 22:57 ` Lukasz Majewski
2017-10-29 22:59 ` Marek Vasut
2017-10-13 8:08 ` [U-Boot] [PATCH v3 07/20] arm: socfpga: Fix with the correct polling status bit tien.fong.chee at intel.com
2017-10-16 15:29 ` Dinh Nguyen
2017-10-23 6:49 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 08/20] arm: socfpga: Add drivers for programing FPGA from flash tien.fong.chee at intel.com
2017-10-16 15:33 ` Dinh Nguyen
2017-10-24 5:52 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 09/20] arm: socfpga: Rename the gen5 sdram driver to more specific name tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 10/20] arm: socfpga: Add DRAM bank size initialization function tien.fong.chee at intel.com
2017-10-13 8:08 ` [U-Boot] [PATCH v3 11/20] arm: socfpga: Add DDR driver for Arria 10 tien.fong.chee at intel.com
2017-10-17 3:08 ` Dinh Nguyen
2017-10-23 7:45 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 12/20] configs: Add DDR Kconfig support " tien.fong.chee at intel.com
2017-10-17 3:21 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 13/20] arm: socfpga: Enable SPL memory allocation tien.fong.chee at intel.com
2017-10-17 3:44 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 14/20] arm: socfpga: Improve comments for Intel SoCFPGA program header tien.fong.chee at intel.com
2017-10-20 14:18 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 15/20] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10 tien.fong.chee at intel.com
2017-10-20 14:19 ` Dinh Nguyen
2017-10-13 8:08 ` [U-Boot] [PATCH v3 16/20] arm: socfpga: Adding clock frequency info for U-boot tien.fong.chee at intel.com
2017-10-20 14:29 ` Dinh Nguyen
2017-10-23 8:02 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 17/20] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot tien.fong.chee at intel.com
2017-10-20 14:33 ` Dinh Nguyen
2017-10-23 8:13 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 18/20] arm: socfpga: Enable function visible to other file tien.fong.chee at intel.com
2017-10-20 14:39 ` Dinh Nguyen
2017-10-23 8:19 ` Chee, Tien Fong
2017-10-23 14:24 ` Dinh Nguyen
2017-10-24 5:11 ` Chee, Tien Fong
2017-10-13 8:08 ` [U-Boot] [PATCH v3 19/20] arm: socfpga: Enable DDR working tien.fong.chee at intel.com
2017-10-20 15:11 ` Dinh Nguyen
2017-10-24 5:34 ` Chee, Tien Fong [this message]
2017-10-13 8:08 ` [U-Boot] [PATCH v3 20/20] arm: socfpga: Enable SPL booting U-boot tien.fong.chee at intel.com
2017-10-20 15:21 ` Dinh Nguyen
2017-10-24 5:37 ` Chee, Tien Fong
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