From mboxrd@z Thu Jan  1 00:00:00 1970
From: See, Chin Liang <chin.liang.see@intel.com>
Date: Tue, 17 Apr 2018 08:52:53 +0000
Subject: [U-Boot] [PATCH 1/5] ARM: socfpga: Add boot trampoline for
 Arria10
In-Reply-To: <6d918803-23da-8e25-f6bd-619404e01e15@gmail.com>
References: <20180415133704.18950-1-marex@denx.de>
 <1523954412.2582.13.camel@intel.com>
 <6d918803-23da-8e25-f6bd-619404e01e15@gmail.com>
Message-ID: <1523955172.2582.17.camel@intel.com>
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To: u-boot@lists.denx.de

On Tue, 2018-04-17 at 10:46 +0200, Marek Vasut wrote:
> On 04/17/2018 10:40 AM, See, Chin Liang wrote:
> > 
> > Hi Marek,
> > 
> > On Sun, 2018-04-15 at 15:37 +0200, Marek Vasut wrote:
> > > 
> > > The Arria10 uses slightly different boot image header than the
> > > Gen5
> > > SoCs,
> > > in particular the header itself contains an offset from the start
> > > of
> > > the
> > > header to which the Arria10 jumps. This offset must not be
> > > negative,
> > > yet
> > > the header is placed at offset 0x40 of the bootable binary.
> > > Therefore, to
> > > jump into U-Boot, add a trampoline just past the Arria10 boot
> > > header
> > > and
> > > point to this trampoline at fixed offset from the header
> > > generated
> > > using
> > > the mkimage -T socfpgaimage_v1 . Note that it is not needed to
> > > jump
> > > back
> > > to offset 0x0 of the image, it is possible to jump directly at
> > > the
> > > reset
> > > label and save processing two instructions.
> > > 
> > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > ---
> > >  arch/arm/mach-socfpga/include/mach/boot0.h | 4 ++--
> > >  1 file changed, 2 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > index d6b9435d33..06bbe27d2c 100644
> > > --- a/arch/arm/mach-socfpga/include/mach/boot0.h
> > > +++ b/arch/arm/mach-socfpga/include/mach/boot0.h
> > > @@ -18,10 +18,10 @@ _start:
> > >  	.word	0xcafec0d3;	/* Checksum, zero-pad */
> > >  	nop;
> > >  
> > > -	b reset;		/* SoCFPGA jumps here */
> > > -	nop;
> > > +	b reset;		/* SoCFPGA Gen5 jumps here */
> > >  	nop;
> > >  	nop;
> > > +	b reset;		/* SoCFPGA Gen10 trampoline */
> > Our mkpimage tools from SOCEDS is using 0x14 as offset. Wonder can
> > we
> > standardize that by using 0x14 instead of proposed 0x18 in this
> > patch?
> What difference does it make, the entire image is generated during
> the
> build anyway ? This patch uses offset 0x1c, but what is the reason
> for
> address 0x14 in your proprietary tool, is there one ?

Our A10 header ended at 0x13 today. Hence we are continuing the code at
0x14 without any spacing.

While for 0x1c, should it be 3 nop?

Thanks
Chin Liang

>