[U-Boot] [PATCH v1 01/16] arm: socfpga: stratix10: Add base address map for Statix10 SoC

Marek Vasut
2018-04-20T10:59:59Z

On 04/20/2018 05:22 PM, Ley Foon Tan wrote:
> On Thu, 2018-04-19 at 05:02 +0200, Marek Vasut wrote:
>> On 04/19/2018 11:50 AM, Ley Foon Tan wrote:
>>>
>>> Add the base address map for Statix10 SoC
>>>
>>> Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
>>> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
>>> ---
>>>  arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   38
>>> ++++++++++++++++++++
>>>  1 files changed, 38 insertions(+), 0 deletions(-)
>>>  create mode 100644 arch/arm/mach-
>>> socfpga/include/mach/base_addr_s10.h
>>>
>>> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>>> b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>>> new file mode 100644
>>> index 0000000..e18d2bf
>>> --- /dev/null
>>> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
>>> @@ -0,0 +1,38 @@
>>> +/* SPDX-License-Identifier: GPL-2.0
>>> + *
>>> + * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
>>> + *
>>> + */
>>> +
>>> +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
>>> +#define _SOCFPGA_S10_BASE_HARDWARE_H_
>>> +
>>> +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
>>> +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
>>> +#define SOCFPGA_SDR_ADDRESS 0xf8011000
>>> +#define SOCFPGA_SMMU_ADDRESS 0xfa000000
>>> +#define SOCFPGA_MAILBOX_ADDRESS 0xffA30000
>>> +#define SOCFPGA_UART0_ADDRESS 0xffc02000
>>> +#define SOCFPGA_UART1_ADDRESS 0xffc02100
>>> +#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
>>> +#define SOCFPGA_L4WD1_ADDRESS 0xffd00300
>>> +#define SOCFPGA_L4WD2_ADDRESS 0xffd00400
>>> +#define SOCFPGA_L4WD3_ADDRESS 0xffd00500
>>> +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
>>> +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000
>>> +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
>>> +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
>>> +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
>>> +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
>>> +#define SOCFPGA_FIREWALL_L4_PER 0xffd21000
>>> +#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100
>>> +#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200
>>> +#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300
>>> +#define SOCFPGA_FIREWALL_TCU 0xffd21400
>>> +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
>>> +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
>>> +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
>>> +#define GICD_BASE 0xfffc1000
>>> +#define GICC_BASE 0xfffc2000
>> How much of this can come from DT ?
>>
>
> Just found out Dinh already upstreamed this patch. BTW, we will try to
> use DT when it is possible.

It is possible since years ago :-)

--
Best regards,
Marek Vasut