From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Shevchenko Date: Mon, 23 Apr 2018 11:22:44 +0300 Subject: [U-Boot] [PATCH v6 1/2] x86: Add TSC-specific timer functions In-Reply-To: <20180420180047.GB2940@intel.com> References: <269698c303c3da454b34f149d4a3562fc57091f2.1523570597.git.ivan.gorinov@intel.com> <1524227108.21176.462.camel@linux.intel.com> <20180420180047.GB2940@intel.com> Message-ID: <1524471764.21176.483.camel@linux.intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On Fri, 2018-04-20 at 11:00 -0700, Ivan Gorinov wrote: > On Fri, Apr 20, 2018 at 06:25:08AM -0600, Andy Shevchenko wrote: > > > - while (rdtsc() < final_tsc) > > > - ; > > > + while (rdtsc() - start_tsc < ticks); > > > > I would rather preserve existing style. > > OK. Existing style does not correctly handle overflow, > but for a 64-bit counter it's a very unlikely event. You didn't get me. I'm just talking about style, not about functionality. See above for lines I left in this reply. -- Andy Shevchenko Intel Finland Oy