From: See, Chin Liang <chin.liang.see@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH] ARM: socfpga: Make DRAM node available in SPL
Date: Thu, 31 May 2018 09:53:00 +0000 [thread overview]
Message-ID: <1527846829.3004.5.camel@intel.com> (raw)
In-Reply-To: <20180529163843.29608-1-marex@denx.de>
On Tue, 2018-05-29 at 18:38 +0200, Marek Vasut wrote:
> The SPL can also parse the DRAM configuration node to figure out the
> memory layout, make sure it is available.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> ---
> arch/arm/dts/socfpga_arria10_socdk.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> index d7616dd1c5..3f59f02577 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> @@ -34,6 +34,7 @@
> name = "memory";
> device_type = "memory";
> reg = <0x0 0x40000000>; /* 1GB */
> + u-boot,dm-pre-reloc;
> };
>
> a10leds {
Reviewed-by: Chin Liang See <chin.liang.see@intel.com>
Thanks
Chin Liang
prev parent reply other threads:[~2018-05-31 9:53 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-29 16:38 [U-Boot] [PATCH] ARM: socfpga: Make DRAM node available in SPL Marek Vasut
2018-05-31 9:53 ` See, Chin Liang [this message]
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