From mboxrd@z Thu Jan  1 00:00:00 1970
From: See, Chin Liang <chin.liang.see@intel.com>
Date: Thu, 31 May 2018 09:53:00 +0000
Subject: [U-Boot] [PATCH] ARM: socfpga: Make DRAM node available in SPL
In-Reply-To: <20180529163843.29608-1-marex@denx.de>
References: <20180529163843.29608-1-marex@denx.de>
Message-ID: <1527846829.3004.5.camel@intel.com>
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To: u-boot@lists.denx.de

On Tue, 2018-05-29 at 18:38 +0200, Marek Vasut wrote:
> The SPL can also parse the DRAM configuration node to figure out the
> memory layout, make sure it is available.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  arch/arm/dts/socfpga_arria10_socdk.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> index d7616dd1c5..3f59f02577 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk.dtsi
> +++ b/arch/arm/dts/socfpga_arria10_socdk.dtsi
> @@ -34,6 +34,7 @@
>  		name = "memory";
>  		device_type = "memory";
>  		reg = <0x0 0x40000000>; /* 1GB */
> +		u-boot,dm-pre-reloc;
>  	};
>  
>  	a10leds {

Reviewed-by: Chin Liang See <chin.liang.see@intel.com>

Thanks
Chin Liang