public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed
* [U-Boot] [PATCH] ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10
@ 2018-05-29 16:36 Marek Vasut
  2018-05-31  9:56 ` See, Chin Liang
  0 siblings, 1 reply; 2+ messages in thread
From: Marek Vasut @ 2018-05-29 16:36 UTC (permalink / raw)
  To: u-boot

This function was never used in SPL and the default implementation of
dram_bank_mmu_setup() does the same thing. The only difference is the
part which configures OCRAM as cachable, which doesn't really work as
it covers more than the OCRAM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
---
 drivers/ddr/altera/sdram_arria10.c | 25 -------------------------
 1 file changed, 25 deletions(-)

diff --git a/drivers/ddr/altera/sdram_arria10.c b/drivers/ddr/altera/sdram_arria10.c
index 706a038b88..1f2b7f4819 100644
--- a/drivers/ddr/altera/sdram_arria10.c
+++ b/drivers/ddr/altera/sdram_arria10.c
@@ -713,28 +713,3 @@ int ddr_calibration_sequence(void)
 
 	return 0;
 }
-
-void dram_bank_mmu_setup(int bank)
-{
-	bd_t *bd = gd->bd;
-	int	i;
-
-	debug("%s: bank: %d\n", __func__, bank);
-	for (i = bd->bi_dram[bank].start >> 20;
-	     i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
-	     i++) {
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-		set_section_dcache(i, DCACHE_WRITETHROUGH);
-#else
-		set_section_dcache(i, DCACHE_WRITEBACK);
-#endif
-	}
-
-	/* same as above but just that we would want cacheable for ocram too */
-	i = CONFIG_SYS_INIT_RAM_ADDR >> 20;
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
-	set_section_dcache(i, DCACHE_WRITETHROUGH);
-#else
-	set_section_dcache(i, DCACHE_WRITEBACK);
-#endif
-}
-- 
2.17.0

^ permalink raw reply related	[flat|nested] 2+ messages in thread

* [U-Boot] [PATCH] ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10
  2018-05-29 16:36 [U-Boot] [PATCH] ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 Marek Vasut
@ 2018-05-31  9:56 ` See, Chin Liang
  0 siblings, 0 replies; 2+ messages in thread
From: See, Chin Liang @ 2018-05-31  9:56 UTC (permalink / raw)
  To: u-boot

On Tue, 2018-05-29 at 18:36 +0200, Marek Vasut wrote:
> This function was never used in SPL and the default implementation of
> dram_bank_mmu_setup() does the same thing. The only difference is the
> part which configures OCRAM as cachable, which doesn't really work as
> it covers more than the OCRAM.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> ---
>  drivers/ddr/altera/sdram_arria10.c | 25 -------------------------
>  1 file changed, 25 deletions(-)
> 


Reviewed-by: Chin Liang See <chin.liang.see@intel.com>

Thanks
Chin Liang

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2018-05-31  9:56 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-05-29 16:36 [U-Boot] [PATCH] ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10 Marek Vasut
2018-05-31  9:56 ` See, Chin Liang

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox