From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ley Foon Tan Date: Thu, 09 Aug 2018 16:27:52 +0800 Subject: [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only In-Reply-To: <20180808201124.19826-2-marex@denx.de> References: <20180808201124.19826-1-marex@denx.de> <20180808201124.19826-2-marex@denx.de> Message-ID: <1533803272.38452.9.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote: > The L4SP and MMC clock precalculation is specific to Gen5, it is not > needed on Arria10/Stratix10. Isolate it to Gen5 until there is a > proper > clock driver for Gen5, at which point this will go away completely. > > Signed-off-by: Marek Vasut > Cc: Chin Liang See > Cc: Dinh Nguyen > Cc: Ley Foon Tan > --- >  arch/arm/mach-socfpga/clock_manager.c | 2 ++ >  1 file changed, 2 insertions(+) > > diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach- > socfpga/clock_manager.c > index 59ede59b59..9f3c643df8 100644 > --- a/arch/arm/mach-socfpga/clock_manager.c > +++ b/arch/arm/mach-socfpga/clock_manager.c > @@ -42,9 +42,11 @@ int cm_wait_for_fsm(void) >   >  int set_cpu_clk_info(void) >  { > +#if defined(CONFIG_TARGET_SOCFPGA_GEN5) >   /* Calculate the clock frequencies required for drivers */ >   cm_get_l4_sp_clk_hz(); >   cm_get_mmc_controller_clk_hz(); > +#endif >   >   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000; >   gd->bd->bi_dsp_freq = 0; Reviewed-by: Ley Foon Tan