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From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10
Date: Thu, 09 Aug 2018 16:28:24 +0800	[thread overview]
Message-ID: <1533803304.38452.10.camel@intel.com> (raw)
In-Reply-To: <20180808201124.19826-3-marex@denx.de>

On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
> The variables removed in this patch are never used, they are only
> ever
> assigned and then waste precious memory. Drop both the assignment and
> the variables.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
>  arch/arm/mach-socfpga/clock_manager_arria10.c | 19 ++---------------
> --
>  1 file changed, 2 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> b/arch/arm/mach-socfpga/clock_manager_arria10.c
> index 59d3f9d50a..6b5c7b1ec4 100644
> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> @@ -17,10 +17,6 @@ static const struct socfpga_clock_manager
> *clock_manager_base =
>  static u32 eosc1_hz;
>  static u32 cb_intosc_hz;
>  static u32 f2s_free_hz;
> -static u32 cm_l4_main_clk_hz;
> -static u32 cm_l4_sp_clk_hz;
> -static u32 cm_l4_mp_clk_hz;
> -static u32 cm_l4_sys_free_clk_hz;
>  
>  struct mainpll_cfg {
>  	u32 vco0_psrc;
> @@ -969,18 +965,7 @@ int cm_basic_init(const void *blob)
>  	if (rval)
>  		return rval;
>  
> -	rval =  cm_full_cfg(&main_cfg, &per_cfg);
> -
> -	cm_l4_main_clk_hz =
> -		cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB
> );
> -
> -	cm_l4_mp_clk_hz =
> cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
> -
> -	cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz();
> -
> -	cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4;
> -
> -	return rval;
> +	return cm_full_cfg(&main_cfg, &per_cfg);
>  } 
>  unsigned long cm_get_mpu_clk_hz(void)
> @@ -1177,5 +1162,5 @@ void cm_print_clock_quick_summary(void)
>  	printf("L4 MP       %8d kHz\n",
>  	       cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) /
> 1000);
>  	printf("L4 SP       %8d kHz\n", cm_get_l4_sp_clk_hz() /
> 1000);
> -	printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz /
> 1000);
> +	printf("L4 sys free %8d kHz\n", cm_get_noc_clk_hz() / 4000);
>  }

Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>

  reply	other threads:[~2018-08-09  8:28 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-08 20:11 [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Marek Vasut
2018-08-08 20:11 ` [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only Marek Vasut
2018-08-09  8:27   ` Ley Foon Tan
2018-08-08 20:11 ` [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10 Marek Vasut
2018-08-09  8:28   ` Ley Foon Tan [this message]
2018-08-09  8:23 ` [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Ley Foon Tan
2018-08-09  8:37   ` Marek Vasut
2018-08-09  9:10     ` Ley Foon Tan
2018-08-09  9:40       ` Marek Vasut

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