From: Ley Foon Tan <ley.foon.tan@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM
Date: Thu, 09 Aug 2018 17:10:55 +0800 [thread overview]
Message-ID: <1533805855.39624.3.camel@intel.com> (raw)
In-Reply-To: <b1cc2174-2cac-1523-bb55-2e1aeb3b6dee@denx.de>
On Thu, 2018-08-09 at 10:37 +0200, Marek Vasut wrote:
> On 08/09/2018 10:23 AM, Ley Foon Tan wrote:
> >
> > On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
> > >
> > > Bind fixed clock driver to the base clock instantiated in the
> > > handoff
> > > DT and use DM clock framework to get their clock rate. This
> > > replaces
> > > the ad-hoc DT parsing present thus far.
> > >
> > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> > > ---
> > > arch/arm/mach-socfpga/Kconfig | 2 ++
> > > arch/arm/mach-socfpga/clock_manager_arria10.c | 41
> > > +++++++++++++++++++--------
> > > 2 files changed, 31 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> > > socfpga/Kconfig
> > > index 5c1df2cf1f..2655289a72 100644
> > > --- a/arch/arm/mach-socfpga/Kconfig
> > > +++ b/arch/arm/mach-socfpga/Kconfig
> > > @@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10
> > > bool
> > > select ALTERA_SDRAM
> > > select SPL_BOARD_INIT if SPL
> > > + select CLK
> > > + select SPL_CLK if SPL
> > >
> > > config TARGET_SOCFPGA_CYCLONE5
> > > bool
> > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > index defa2f6261..59d3f9d50a 100644
> > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > @@ -7,6 +7,8 @@
> > > #include <fdtdec.h>
> > > #include <asm/io.h>
> > > #include <dm.h>
> > > +#include <clk.h>
> > > +#include <dm/device-internal.h>
> > > #include <asm/arch/clock_manager.h>
> > >
> > > static const struct socfpga_clock_manager *clock_manager_base =
> > > @@ -141,9 +143,9 @@ struct strtopu32 {
> > > };
> > >
> > > const struct strtopu32 dt_to_val[] = {
> > > - { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz},
> > > - { "/clocks/altera_arria10_hps_cb_intosc_ls",
> > > &cb_intosc_hz},
> > > - { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz},
> > > + { "altera_arria10_hps_eosc1", &eosc1_hz },
> > > + { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
> > > + { "altera_arria10_hps_f2h_free", &f2s_free_hz },
> > > };
> > >
> > > static int of_to_struct(const void *blob, int node, const struct
> > > strtou32 *cfg_tab,
> > > @@ -163,28 +165,43 @@ static int of_to_struct(const void *blob,
> > > int
> > > node, const struct strtou32 *cfg_t
> > > return 0;
> > > }
> > >
> > > -static void of_get_input_clks(const void *blob)
> > > +static int of_get_input_clks(const void *blob)
> > > {
> > > - int node, i;
> > > + struct udevice *dev;
> > > + struct clk clk;
> > > + int i, ret;
> > >
> > > for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
> > > - node = fdt_path_offset(blob, dt_to_val[i].str);
> > > + memset(&clk, 0, sizeof(clk));
> > >
> > > - if (node < 0)
> > > - continue;
> > > + ret = uclass_get_device_by_name(UCLASS_CLK,
> > > dt_to_val[i].str,
> > > + &dev);
> > > + if (ret)
> > > + return ret;
> > >
> > > - fdtdec_get_int_array(blob, node, "clock-
> > > frequency",
> > > - dt_to_val[i].p, 1);
> > > + ret = device_probe(dev);
> > uclass_get_device_by_name() will call to device_probe() function.
> > So,
> > can remove this.
> Are you sure about that ? Why so ?
It will call to device_probe() function eventually. See code in http://
git.denx.de/?p=u-boot.git;a=blob;f=drivers/core/uclass.c
The sequence:
uclass_get_device_by_name() --> uclass_get_device_tail() --
> device_probe()
I used uclass_get_device() function before, it has same implementation
as uclass_get_device_by_name(). We don't need call to device_probe()
manually.
Regards
Ley Foon
next prev parent reply other threads:[~2018-08-09 9:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-08 20:11 [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Marek Vasut
2018-08-08 20:11 ` [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only Marek Vasut
2018-08-09 8:27 ` Ley Foon Tan
2018-08-08 20:11 ` [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10 Marek Vasut
2018-08-09 8:28 ` Ley Foon Tan
2018-08-09 8:23 ` [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Ley Foon Tan
2018-08-09 8:37 ` Marek Vasut
2018-08-09 9:10 ` Ley Foon Tan [this message]
2018-08-09 9:40 ` Marek Vasut
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