* [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM
@ 2018-08-08 20:11 Marek Vasut
2018-08-08 20:11 ` [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only Marek Vasut
` (2 more replies)
0 siblings, 3 replies; 9+ messages in thread
From: Marek Vasut @ 2018-08-08 20:11 UTC (permalink / raw)
To: u-boot
Bind fixed clock driver to the base clock instantiated in the handoff
DT and use DM clock framework to get their clock rate. This replaces
the ad-hoc DT parsing present thus far.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/Kconfig | 2 ++
arch/arm/mach-socfpga/clock_manager_arria10.c | 41 +++++++++++++++++++--------
2 files changed, 31 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 5c1df2cf1f..2655289a72 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10
bool
select ALTERA_SDRAM
select SPL_BOARD_INIT if SPL
+ select CLK
+ select SPL_CLK if SPL
config TARGET_SOCFPGA_CYCLONE5
bool
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index defa2f6261..59d3f9d50a 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -7,6 +7,8 @@
#include <fdtdec.h>
#include <asm/io.h>
#include <dm.h>
+#include <clk.h>
+#include <dm/device-internal.h>
#include <asm/arch/clock_manager.h>
static const struct socfpga_clock_manager *clock_manager_base =
@@ -141,9 +143,9 @@ struct strtopu32 {
};
const struct strtopu32 dt_to_val[] = {
- { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz},
- { "/clocks/altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz},
- { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz},
+ { "altera_arria10_hps_eosc1", &eosc1_hz },
+ { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
+ { "altera_arria10_hps_f2h_free", &f2s_free_hz },
};
static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_tab,
@@ -163,28 +165,43 @@ static int of_to_struct(const void *blob, int node, const struct strtou32 *cfg_t
return 0;
}
-static void of_get_input_clks(const void *blob)
+static int of_get_input_clks(const void *blob)
{
- int node, i;
+ struct udevice *dev;
+ struct clk clk;
+ int i, ret;
for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
- node = fdt_path_offset(blob, dt_to_val[i].str);
+ memset(&clk, 0, sizeof(clk));
- if (node < 0)
- continue;
+ ret = uclass_get_device_by_name(UCLASS_CLK, dt_to_val[i].str,
+ &dev);
+ if (ret)
+ return ret;
- fdtdec_get_int_array(blob, node, "clock-frequency",
- dt_to_val[i].p, 1);
+ ret = device_probe(dev);
+ if (ret)
+ return ret;
+
+ ret = clk_request(dev, &clk);
+ if (ret)
+ return ret;
+
+ *dt_to_val[i].p = clk_get_rate(&clk);
}
+
+ return 0;
}
static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
struct perpll_cfg *per_cfg)
{
- int node, child, len;
+ int ret, node, child, len;
const char *node_name;
- of_get_input_clks(blob);
+ ret = of_get_input_clks(blob);
+ if (ret)
+ return ret;
node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK_INIT);
--
2.16.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
2018-08-08 20:11 [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Marek Vasut
@ 2018-08-08 20:11 ` Marek Vasut
2018-08-09 8:27 ` Ley Foon Tan
2018-08-08 20:11 ` [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10 Marek Vasut
2018-08-09 8:23 ` [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Ley Foon Tan
2 siblings, 1 reply; 9+ messages in thread
From: Marek Vasut @ 2018-08-08 20:11 UTC (permalink / raw)
To: u-boot
The L4SP and MMC clock precalculation is specific to Gen5, it is not
needed on Arria10/Stratix10. Isolate it to Gen5 until there is a proper
clock driver for Gen5, at which point this will go away completely.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/clock_manager.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c
index 59ede59b59..9f3c643df8 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -42,9 +42,11 @@ int cm_wait_for_fsm(void)
int set_cpu_clk_info(void)
{
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
/* Calculate the clock frequencies required for drivers */
cm_get_l4_sp_clk_hz();
cm_get_mmc_controller_clk_hz();
+#endif
gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
gd->bd->bi_dsp_freq = 0;
--
2.16.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10
2018-08-08 20:11 [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Marek Vasut
2018-08-08 20:11 ` [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only Marek Vasut
@ 2018-08-08 20:11 ` Marek Vasut
2018-08-09 8:28 ` Ley Foon Tan
2018-08-09 8:23 ` [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Ley Foon Tan
2 siblings, 1 reply; 9+ messages in thread
From: Marek Vasut @ 2018-08-08 20:11 UTC (permalink / raw)
To: u-boot
The variables removed in this patch are never used, they are only ever
assigned and then waste precious memory. Drop both the assignment and
the variables.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
---
arch/arm/mach-socfpga/clock_manager_arria10.c | 19 ++-----------------
1 file changed, 2 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 59d3f9d50a..6b5c7b1ec4 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -17,10 +17,6 @@ static const struct socfpga_clock_manager *clock_manager_base =
static u32 eosc1_hz;
static u32 cb_intosc_hz;
static u32 f2s_free_hz;
-static u32 cm_l4_main_clk_hz;
-static u32 cm_l4_sp_clk_hz;
-static u32 cm_l4_mp_clk_hz;
-static u32 cm_l4_sys_free_clk_hz;
struct mainpll_cfg {
u32 vco0_psrc;
@@ -969,18 +965,7 @@ int cm_basic_init(const void *blob)
if (rval)
return rval;
- rval = cm_full_cfg(&main_cfg, &per_cfg);
-
- cm_l4_main_clk_hz =
- cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
-
- cm_l4_mp_clk_hz = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
-
- cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz();
-
- cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4;
-
- return rval;
+ return cm_full_cfg(&main_cfg, &per_cfg);
}
unsigned long cm_get_mpu_clk_hz(void)
@@ -1177,5 +1162,5 @@ void cm_print_clock_quick_summary(void)
printf("L4 MP %8d kHz\n",
cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000);
printf("L4 SP %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
- printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz / 1000);
+ printf("L4 sys free %8d kHz\n", cm_get_noc_clk_hz() / 4000);
}
--
2.16.2
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM
2018-08-08 20:11 [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Marek Vasut
2018-08-08 20:11 ` [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only Marek Vasut
2018-08-08 20:11 ` [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10 Marek Vasut
@ 2018-08-09 8:23 ` Ley Foon Tan
2018-08-09 8:37 ` Marek Vasut
2 siblings, 1 reply; 9+ messages in thread
From: Ley Foon Tan @ 2018-08-09 8:23 UTC (permalink / raw)
To: u-boot
On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
> Bind fixed clock driver to the base clock instantiated in the handoff
> DT and use DM clock framework to get their clock rate. This replaces
> the ad-hoc DT parsing present thus far.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
> arch/arm/mach-socfpga/Kconfig | 2 ++
> arch/arm/mach-socfpga/clock_manager_arria10.c | 41
> +++++++++++++++++++--------
> 2 files changed, 31 insertions(+), 12 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> socfpga/Kconfig
> index 5c1df2cf1f..2655289a72 100644
> --- a/arch/arm/mach-socfpga/Kconfig
> +++ b/arch/arm/mach-socfpga/Kconfig
> @@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10
> bool
> select ALTERA_SDRAM
> select SPL_BOARD_INIT if SPL
> + select CLK
> + select SPL_CLK if SPL
>
> config TARGET_SOCFPGA_CYCLONE5
> bool
> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> b/arch/arm/mach-socfpga/clock_manager_arria10.c
> index defa2f6261..59d3f9d50a 100644
> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> @@ -7,6 +7,8 @@
> #include <fdtdec.h>
> #include <asm/io.h>
> #include <dm.h>
> +#include <clk.h>
> +#include <dm/device-internal.h>
> #include <asm/arch/clock_manager.h>
>
> static const struct socfpga_clock_manager *clock_manager_base =
> @@ -141,9 +143,9 @@ struct strtopu32 {
> };
>
> const struct strtopu32 dt_to_val[] = {
> - { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz},
> - { "/clocks/altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz},
> - { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz},
> + { "altera_arria10_hps_eosc1", &eosc1_hz },
> + { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
> + { "altera_arria10_hps_f2h_free", &f2s_free_hz },
> };
>
> static int of_to_struct(const void *blob, int node, const struct
> strtou32 *cfg_tab,
> @@ -163,28 +165,43 @@ static int of_to_struct(const void *blob, int
> node, const struct strtou32 *cfg_t
> return 0;
> }
>
> -static void of_get_input_clks(const void *blob)
> +static int of_get_input_clks(const void *blob)
> {
> - int node, i;
> + struct udevice *dev;
> + struct clk clk;
> + int i, ret;
>
> for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
> - node = fdt_path_offset(blob, dt_to_val[i].str);
> + memset(&clk, 0, sizeof(clk));
>
> - if (node < 0)
> - continue;
> + ret = uclass_get_device_by_name(UCLASS_CLK,
> dt_to_val[i].str,
> + &dev);
> + if (ret)
> + return ret;
>
> - fdtdec_get_int_array(blob, node, "clock-frequency",
> - dt_to_val[i].p, 1);
> + ret = device_probe(dev);
uclass_get_device_by_name() will call to device_probe() function. So,
can remove this.
> + if (ret)
> + return ret;
> +
> + ret = clk_request(dev, &clk);
> + if (ret)
> + return ret;
> +
> + *dt_to_val[i].p = clk_get_rate(&clk);
> }
> +
> + return 0;
> }
>
> static int of_get_clk_cfg(const void *blob, struct mainpll_cfg
> *main_cfg,
> struct perpll_cfg *per_cfg)
> {
> - int node, child, len;
> + int ret, node, child, len;
> const char *node_name;
>
> - of_get_input_clks(blob);
> + ret = of_get_input_clks(blob);
> + if (ret)
> + return ret;
>
> node = fdtdec_next_compatible(blob, 0,
> COMPAT_ALTERA_SOCFPGA_CLK_INIT);
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only
2018-08-08 20:11 ` [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only Marek Vasut
@ 2018-08-09 8:27 ` Ley Foon Tan
0 siblings, 0 replies; 9+ messages in thread
From: Ley Foon Tan @ 2018-08-09 8:27 UTC (permalink / raw)
To: u-boot
On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
> The L4SP and MMC clock precalculation is specific to Gen5, it is not
> needed on Arria10/Stratix10. Isolate it to Gen5 until there is a
> proper
> clock driver for Gen5, at which point this will go away completely.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
> arch/arm/mach-socfpga/clock_manager.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-
> socfpga/clock_manager.c
> index 59ede59b59..9f3c643df8 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -42,9 +42,11 @@ int cm_wait_for_fsm(void)
>
> int set_cpu_clk_info(void)
> {
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> /* Calculate the clock frequencies required for drivers */
> cm_get_l4_sp_clk_hz();
> cm_get_mmc_controller_clk_hz();
> +#endif
>
> gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
> gd->bd->bi_dsp_freq = 0;
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10
2018-08-08 20:11 ` [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10 Marek Vasut
@ 2018-08-09 8:28 ` Ley Foon Tan
0 siblings, 0 replies; 9+ messages in thread
From: Ley Foon Tan @ 2018-08-09 8:28 UTC (permalink / raw)
To: u-boot
On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
> The variables removed in this patch are never used, they are only
> ever
> assigned and then waste precious memory. Drop both the assignment and
> the variables.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> ---
> arch/arm/mach-socfpga/clock_manager_arria10.c | 19 ++---------------
> --
> 1 file changed, 2 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> b/arch/arm/mach-socfpga/clock_manager_arria10.c
> index 59d3f9d50a..6b5c7b1ec4 100644
> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> @@ -17,10 +17,6 @@ static const struct socfpga_clock_manager
> *clock_manager_base =
> static u32 eosc1_hz;
> static u32 cb_intosc_hz;
> static u32 f2s_free_hz;
> -static u32 cm_l4_main_clk_hz;
> -static u32 cm_l4_sp_clk_hz;
> -static u32 cm_l4_mp_clk_hz;
> -static u32 cm_l4_sys_free_clk_hz;
>
> struct mainpll_cfg {
> u32 vco0_psrc;
> @@ -969,18 +965,7 @@ int cm_basic_init(const void *blob)
> if (rval)
> return rval;
>
> - rval = cm_full_cfg(&main_cfg, &per_cfg);
> -
> - cm_l4_main_clk_hz =
> - cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB
> );
> -
> - cm_l4_mp_clk_hz =
> cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
> -
> - cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz();
> -
> - cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4;
> -
> - return rval;
> + return cm_full_cfg(&main_cfg, &per_cfg);
> }
> unsigned long cm_get_mpu_clk_hz(void)
> @@ -1177,5 +1162,5 @@ void cm_print_clock_quick_summary(void)
> printf("L4 MP %8d kHz\n",
> cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) /
> 1000);
> printf("L4 SP %8d kHz\n", cm_get_l4_sp_clk_hz() /
> 1000);
> - printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz /
> 1000);
> + printf("L4 sys free %8d kHz\n", cm_get_noc_clk_hz() / 4000);
> }
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM
2018-08-09 8:23 ` [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Ley Foon Tan
@ 2018-08-09 8:37 ` Marek Vasut
2018-08-09 9:10 ` Ley Foon Tan
0 siblings, 1 reply; 9+ messages in thread
From: Marek Vasut @ 2018-08-09 8:37 UTC (permalink / raw)
To: u-boot
On 08/09/2018 10:23 AM, Ley Foon Tan wrote:
> On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
>> Bind fixed clock driver to the base clock instantiated in the handoff
>> DT and use DM clock framework to get their clock rate. This replaces
>> the ad-hoc DT parsing present thus far.
>>
>> Signed-off-by: Marek Vasut <marex@denx.de>
>> Cc: Chin Liang See <chin.liang.see@intel.com>
>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
>> ---
>> arch/arm/mach-socfpga/Kconfig | 2 ++
>> arch/arm/mach-socfpga/clock_manager_arria10.c | 41
>> +++++++++++++++++++--------
>> 2 files changed, 31 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
>> socfpga/Kconfig
>> index 5c1df2cf1f..2655289a72 100644
>> --- a/arch/arm/mach-socfpga/Kconfig
>> +++ b/arch/arm/mach-socfpga/Kconfig
>> @@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10
>> bool
>> select ALTERA_SDRAM
>> select SPL_BOARD_INIT if SPL
>> + select CLK
>> + select SPL_CLK if SPL
>>
>> config TARGET_SOCFPGA_CYCLONE5
>> bool
>> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
>> b/arch/arm/mach-socfpga/clock_manager_arria10.c
>> index defa2f6261..59d3f9d50a 100644
>> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
>> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>> @@ -7,6 +7,8 @@
>> #include <fdtdec.h>
>> #include <asm/io.h>
>> #include <dm.h>
>> +#include <clk.h>
>> +#include <dm/device-internal.h>
>> #include <asm/arch/clock_manager.h>
>>
>> static const struct socfpga_clock_manager *clock_manager_base =
>> @@ -141,9 +143,9 @@ struct strtopu32 {
>> };
>>
>> const struct strtopu32 dt_to_val[] = {
>> - { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz},
>> - { "/clocks/altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz},
>> - { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz},
>> + { "altera_arria10_hps_eosc1", &eosc1_hz },
>> + { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
>> + { "altera_arria10_hps_f2h_free", &f2s_free_hz },
>> };
>>
>> static int of_to_struct(const void *blob, int node, const struct
>> strtou32 *cfg_tab,
>> @@ -163,28 +165,43 @@ static int of_to_struct(const void *blob, int
>> node, const struct strtou32 *cfg_t
>> return 0;
>> }
>>
>> -static void of_get_input_clks(const void *blob)
>> +static int of_get_input_clks(const void *blob)
>> {
>> - int node, i;
>> + struct udevice *dev;
>> + struct clk clk;
>> + int i, ret;
>>
>> for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
>> - node = fdt_path_offset(blob, dt_to_val[i].str);
>> + memset(&clk, 0, sizeof(clk));
>>
>> - if (node < 0)
>> - continue;
>> + ret = uclass_get_device_by_name(UCLASS_CLK,
>> dt_to_val[i].str,
>> + &dev);
>> + if (ret)
>> + return ret;
>>
>> - fdtdec_get_int_array(blob, node, "clock-frequency",
>> - dt_to_val[i].p, 1);
>> + ret = device_probe(dev);
> uclass_get_device_by_name() will call to device_probe() function. So,
> can remove this.
Are you sure about that ? Why so ?
>> + if (ret)
>> + return ret;
>> +
>> + ret = clk_request(dev, &clk);
>> + if (ret)
>> + return ret;
>> +
>> + *dt_to_val[i].p = clk_get_rate(&clk);
>> }
>> +
>> + return 0;
>> }
>>
>> static int of_get_clk_cfg(const void *blob, struct mainpll_cfg
>> *main_cfg,
>> struct perpll_cfg *per_cfg)
>> {
>> - int node, child, len;
>> + int ret, node, child, len;
>> const char *node_name;
>>
>> - of_get_input_clks(blob);
>> + ret = of_get_input_clks(blob);
>> + if (ret)
>> + return ret;
>>
>> node = fdtdec_next_compatible(blob, 0,
>> COMPAT_ALTERA_SOCFPGA_CLK_INIT);
>>
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM
2018-08-09 8:37 ` Marek Vasut
@ 2018-08-09 9:10 ` Ley Foon Tan
2018-08-09 9:40 ` Marek Vasut
0 siblings, 1 reply; 9+ messages in thread
From: Ley Foon Tan @ 2018-08-09 9:10 UTC (permalink / raw)
To: u-boot
On Thu, 2018-08-09 at 10:37 +0200, Marek Vasut wrote:
> On 08/09/2018 10:23 AM, Ley Foon Tan wrote:
> >
> > On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
> > >
> > > Bind fixed clock driver to the base clock instantiated in the
> > > handoff
> > > DT and use DM clock framework to get their clock rate. This
> > > replaces
> > > the ad-hoc DT parsing present thus far.
> > >
> > > Signed-off-by: Marek Vasut <marex@denx.de>
> > > Cc: Chin Liang See <chin.liang.see@intel.com>
> > > Cc: Dinh Nguyen <dinguyen@kernel.org>
> > > Cc: Ley Foon Tan <ley.foon.tan@intel.com>
> > > ---
> > > arch/arm/mach-socfpga/Kconfig | 2 ++
> > > arch/arm/mach-socfpga/clock_manager_arria10.c | 41
> > > +++++++++++++++++++--------
> > > 2 files changed, 31 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
> > > socfpga/Kconfig
> > > index 5c1df2cf1f..2655289a72 100644
> > > --- a/arch/arm/mach-socfpga/Kconfig
> > > +++ b/arch/arm/mach-socfpga/Kconfig
> > > @@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10
> > > bool
> > > select ALTERA_SDRAM
> > > select SPL_BOARD_INIT if SPL
> > > + select CLK
> > > + select SPL_CLK if SPL
> > >
> > > config TARGET_SOCFPGA_CYCLONE5
> > > bool
> > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > index defa2f6261..59d3f9d50a 100644
> > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > @@ -7,6 +7,8 @@
> > > #include <fdtdec.h>
> > > #include <asm/io.h>
> > > #include <dm.h>
> > > +#include <clk.h>
> > > +#include <dm/device-internal.h>
> > > #include <asm/arch/clock_manager.h>
> > >
> > > static const struct socfpga_clock_manager *clock_manager_base =
> > > @@ -141,9 +143,9 @@ struct strtopu32 {
> > > };
> > >
> > > const struct strtopu32 dt_to_val[] = {
> > > - { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz},
> > > - { "/clocks/altera_arria10_hps_cb_intosc_ls",
> > > &cb_intosc_hz},
> > > - { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz},
> > > + { "altera_arria10_hps_eosc1", &eosc1_hz },
> > > + { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
> > > + { "altera_arria10_hps_f2h_free", &f2s_free_hz },
> > > };
> > >
> > > static int of_to_struct(const void *blob, int node, const struct
> > > strtou32 *cfg_tab,
> > > @@ -163,28 +165,43 @@ static int of_to_struct(const void *blob,
> > > int
> > > node, const struct strtou32 *cfg_t
> > > return 0;
> > > }
> > >
> > > -static void of_get_input_clks(const void *blob)
> > > +static int of_get_input_clks(const void *blob)
> > > {
> > > - int node, i;
> > > + struct udevice *dev;
> > > + struct clk clk;
> > > + int i, ret;
> > >
> > > for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
> > > - node = fdt_path_offset(blob, dt_to_val[i].str);
> > > + memset(&clk, 0, sizeof(clk));
> > >
> > > - if (node < 0)
> > > - continue;
> > > + ret = uclass_get_device_by_name(UCLASS_CLK,
> > > dt_to_val[i].str,
> > > + &dev);
> > > + if (ret)
> > > + return ret;
> > >
> > > - fdtdec_get_int_array(blob, node, "clock-
> > > frequency",
> > > - dt_to_val[i].p, 1);
> > > + ret = device_probe(dev);
> > uclass_get_device_by_name() will call to device_probe() function.
> > So,
> > can remove this.
> Are you sure about that ? Why so ?
It will call to device_probe() function eventually. See code in http://
git.denx.de/?p=u-boot.git;a=blob;f=drivers/core/uclass.c
The sequence:
uclass_get_device_by_name() --> uclass_get_device_tail() --
> device_probe()
I used uclass_get_device() function before, it has same implementation
as uclass_get_device_by_name(). We don't need call to device_probe()
manually.
Regards
Ley Foon
^ permalink raw reply [flat|nested] 9+ messages in thread
* [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM
2018-08-09 9:10 ` Ley Foon Tan
@ 2018-08-09 9:40 ` Marek Vasut
0 siblings, 0 replies; 9+ messages in thread
From: Marek Vasut @ 2018-08-09 9:40 UTC (permalink / raw)
To: u-boot
On 08/09/2018 11:10 AM, Ley Foon Tan wrote:
> On Thu, 2018-08-09 at 10:37 +0200, Marek Vasut wrote:
>> On 08/09/2018 10:23 AM, Ley Foon Tan wrote:
>>>
>>> On Wed, 2018-08-08 at 22:11 +0200, Marek Vasut wrote:
>>>>
>>>> Bind fixed clock driver to the base clock instantiated in the
>>>> handoff
>>>> DT and use DM clock framework to get their clock rate. This
>>>> replaces
>>>> the ad-hoc DT parsing present thus far.
>>>>
>>>> Signed-off-by: Marek Vasut <marex@denx.de>
>>>> Cc: Chin Liang See <chin.liang.see@intel.com>
>>>> Cc: Dinh Nguyen <dinguyen@kernel.org>
>>>> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
>>>> ---
>>>> arch/arm/mach-socfpga/Kconfig | 2 ++
>>>> arch/arm/mach-socfpga/clock_manager_arria10.c | 41
>>>> +++++++++++++++++++--------
>>>> 2 files changed, 31 insertions(+), 12 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-
>>>> socfpga/Kconfig
>>>> index 5c1df2cf1f..2655289a72 100644
>>>> --- a/arch/arm/mach-socfpga/Kconfig
>>>> +++ b/arch/arm/mach-socfpga/Kconfig
>>>> @@ -11,6 +11,8 @@ config TARGET_SOCFPGA_ARRIA10
>>>> bool
>>>> select ALTERA_SDRAM
>>>> select SPL_BOARD_INIT if SPL
>>>> + select CLK
>>>> + select SPL_CLK if SPL
>>>>
>>>> config TARGET_SOCFPGA_CYCLONE5
>>>> bool
>>>> diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>> b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>> index defa2f6261..59d3f9d50a 100644
>>>> --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>> +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>>>> @@ -7,6 +7,8 @@
>>>> #include <fdtdec.h>
>>>> #include <asm/io.h>
>>>> #include <dm.h>
>>>> +#include <clk.h>
>>>> +#include <dm/device-internal.h>
>>>> #include <asm/arch/clock_manager.h>
>>>>
>>>> static const struct socfpga_clock_manager *clock_manager_base =
>>>> @@ -141,9 +143,9 @@ struct strtopu32 {
>>>> };
>>>>
>>>> const struct strtopu32 dt_to_val[] = {
>>>> - { "/clocks/altera_arria10_hps_eosc1", &eosc1_hz},
>>>> - { "/clocks/altera_arria10_hps_cb_intosc_ls",
>>>> &cb_intosc_hz},
>>>> - { "/clocks/altera_arria10_hps_f2h_free", &f2s_free_hz},
>>>> + { "altera_arria10_hps_eosc1", &eosc1_hz },
>>>> + { "altera_arria10_hps_cb_intosc_ls", &cb_intosc_hz },
>>>> + { "altera_arria10_hps_f2h_free", &f2s_free_hz },
>>>> };
>>>>
>>>> static int of_to_struct(const void *blob, int node, const struct
>>>> strtou32 *cfg_tab,
>>>> @@ -163,28 +165,43 @@ static int of_to_struct(const void *blob,
>>>> int
>>>> node, const struct strtou32 *cfg_t
>>>> return 0;
>>>> }
>>>>
>>>> -static void of_get_input_clks(const void *blob)
>>>> +static int of_get_input_clks(const void *blob)
>>>> {
>>>> - int node, i;
>>>> + struct udevice *dev;
>>>> + struct clk clk;
>>>> + int i, ret;
>>>>
>>>> for (i = 0; i < ARRAY_SIZE(dt_to_val); i++) {
>>>> - node = fdt_path_offset(blob, dt_to_val[i].str);
>>>> + memset(&clk, 0, sizeof(clk));
>>>>
>>>> - if (node < 0)
>>>> - continue;
>>>> + ret = uclass_get_device_by_name(UCLASS_CLK,
>>>> dt_to_val[i].str,
>>>> + &dev);
>>>> + if (ret)
>>>> + return ret;
>>>>
>>>> - fdtdec_get_int_array(blob, node, "clock-
>>>> frequency",
>>>> - dt_to_val[i].p, 1);
>>>> + ret = device_probe(dev);
>>> uclass_get_device_by_name() will call to device_probe() function.
>>> So,
>>> can remove this.
>> Are you sure about that ? Why so ?
>
> It will call to device_probe() function eventually. See code in http://
> git.denx.de/?p=u-boot.git;a=blob;f=drivers/core/uclass.c
>
> The sequence:
> uclass_get_device_by_name() --> uclass_get_device_tail() --
>> device_probe()
Ah, you're right. Thanks !
--
Best regards,
Marek Vasut
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-08-09 9:40 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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2018-08-08 20:11 [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Marek Vasut
2018-08-08 20:11 ` [U-Boot] [PATCH 2/3] ARM: socfpga: clk: Make L4SP and MMC clock calculation Gen5 only Marek Vasut
2018-08-09 8:27 ` Ley Foon Tan
2018-08-08 20:11 ` [U-Boot] [PATCH 3/3] ARM: socfpga: clk: Drop unused variables on Arria10 Marek Vasut
2018-08-09 8:28 ` Ley Foon Tan
2018-08-09 8:23 ` [U-Boot] [PATCH 1/3] ARM: socfpga: clk: Obtain handoff base clock via DM Ley Foon Tan
2018-08-09 8:37 ` Marek Vasut
2018-08-09 9:10 ` Ley Foon Tan
2018-08-09 9:40 ` Marek Vasut
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