From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 13/19] riscv: Move trap handler codes to mtrap.S
Date: Tue, 13 Nov 2018 00:22:01 -0800 [thread overview]
Message-ID: <1542097327-6629-14-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com>
Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/cpu/Makefile | 2 +-
arch/riscv/cpu/mtrap.S | 106 ++++++++++++++++++++++++++++++++++++++++++++++++
arch/riscv/cpu/start.S | 82 -------------------------------------
3 files changed, 107 insertions(+), 83 deletions(-)
create mode 100644 arch/riscv/cpu/mtrap.S
diff --git a/arch/riscv/cpu/Makefile b/arch/riscv/cpu/Makefile
index 2cc6757..6bf6f91 100644
--- a/arch/riscv/cpu/Makefile
+++ b/arch/riscv/cpu/Makefile
@@ -4,4 +4,4 @@
extra-y = start.o
-obj-y += cpu.o
+obj-y += cpu.o mtrap.o
diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S
new file mode 100644
index 0000000..ba6462f
--- /dev/null
+++ b/arch/riscv/cpu/mtrap.S
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * M-mode Trap Handler Code for RISC-V Core
+ *
+ * Copyright (c) 2017 Microsemi Corporation.
+ * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
+ *
+ * Copyright (C) 2017 Andes Technology Corporation
+ * Rick Chen, Andes Technology Corporation <rick@andestech.com>
+ *
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/encoding.h>
+
+#ifdef CONFIG_32BIT
+#define LREG lw
+#define SREG sw
+#define REGBYTES 4
+#else
+#define LREG ld
+#define SREG sd
+#define REGBYTES 8
+#endif
+
+ .text
+
+ /* trap entry */
+ .align 2
+ .global trap_entry
+trap_entry:
+ addi sp, sp, -32 * REGBYTES
+ SREG x1, 1 * REGBYTES(sp)
+ SREG x2, 2 * REGBYTES(sp)
+ SREG x3, 3 * REGBYTES(sp)
+ SREG x4, 4 * REGBYTES(sp)
+ SREG x5, 5 * REGBYTES(sp)
+ SREG x6, 6 * REGBYTES(sp)
+ SREG x7, 7 * REGBYTES(sp)
+ SREG x8, 8 * REGBYTES(sp)
+ SREG x9, 9 * REGBYTES(sp)
+ SREG x10, 10 * REGBYTES(sp)
+ SREG x11, 11 * REGBYTES(sp)
+ SREG x12, 12 * REGBYTES(sp)
+ SREG x13, 13 * REGBYTES(sp)
+ SREG x14, 14 * REGBYTES(sp)
+ SREG x15, 15 * REGBYTES(sp)
+ SREG x16, 16 * REGBYTES(sp)
+ SREG x17, 17 * REGBYTES(sp)
+ SREG x18, 18 * REGBYTES(sp)
+ SREG x19, 19 * REGBYTES(sp)
+ SREG x20, 20 * REGBYTES(sp)
+ SREG x21, 21 * REGBYTES(sp)
+ SREG x22, 22 * REGBYTES(sp)
+ SREG x23, 23 * REGBYTES(sp)
+ SREG x24, 24 * REGBYTES(sp)
+ SREG x25, 25 * REGBYTES(sp)
+ SREG x26, 26 * REGBYTES(sp)
+ SREG x27, 27 * REGBYTES(sp)
+ SREG x28, 28 * REGBYTES(sp)
+ SREG x29, 29 * REGBYTES(sp)
+ SREG x30, 30 * REGBYTES(sp)
+ SREG x31, 31 * REGBYTES(sp)
+ csrr a0, mcause
+ csrr a1, mepc
+ mv a2, sp
+ jal handle_trap
+ csrw mepc, a0
+
+ /* Remain in M-mode after mret */
+ li t0, MSTATUS_MPP
+ csrs mstatus, t0
+ LREG x1, 1 * REGBYTES(sp)
+ LREG x2, 2 * REGBYTES(sp)
+ LREG x3, 3 * REGBYTES(sp)
+ LREG x4, 4 * REGBYTES(sp)
+ LREG x5, 5 * REGBYTES(sp)
+ LREG x6, 6 * REGBYTES(sp)
+ LREG x7, 7 * REGBYTES(sp)
+ LREG x8, 8 * REGBYTES(sp)
+ LREG x9, 9 * REGBYTES(sp)
+ LREG x10, 10 * REGBYTES(sp)
+ LREG x11, 11 * REGBYTES(sp)
+ LREG x12, 12 * REGBYTES(sp)
+ LREG x13, 13 * REGBYTES(sp)
+ LREG x14, 14 * REGBYTES(sp)
+ LREG x15, 15 * REGBYTES(sp)
+ LREG x16, 16 * REGBYTES(sp)
+ LREG x17, 17 * REGBYTES(sp)
+ LREG x18, 18 * REGBYTES(sp)
+ LREG x19, 19 * REGBYTES(sp)
+ LREG x20, 20 * REGBYTES(sp)
+ LREG x21, 21 * REGBYTES(sp)
+ LREG x22, 22 * REGBYTES(sp)
+ LREG x23, 23 * REGBYTES(sp)
+ LREG x24, 24 * REGBYTES(sp)
+ LREG x25, 25 * REGBYTES(sp)
+ LREG x26, 26 * REGBYTES(sp)
+ LREG x27, 27 * REGBYTES(sp)
+ LREG x28, 28 * REGBYTES(sp)
+ LREG x29, 29 * REGBYTES(sp)
+ LREG x30, 30 * REGBYTES(sp)
+ LREG x31, 31 * REGBYTES(sp)
+ addi sp, sp, 32 * REGBYTES
+ mret
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 331a534..9858058 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -194,85 +194,3 @@ call_board_init_r:
* jump to it ...
*/
jr t4 /* jump to board_init_r() */
-
-/*
- * trap entry
- */
-.align 2
-trap_entry:
- addi sp, sp, -32*REGBYTES
- SREG x1, 1*REGBYTES(sp)
- SREG x2, 2*REGBYTES(sp)
- SREG x3, 3*REGBYTES(sp)
- SREG x4, 4*REGBYTES(sp)
- SREG x5, 5*REGBYTES(sp)
- SREG x6, 6*REGBYTES(sp)
- SREG x7, 7*REGBYTES(sp)
- SREG x8, 8*REGBYTES(sp)
- SREG x9, 9*REGBYTES(sp)
- SREG x10, 10*REGBYTES(sp)
- SREG x11, 11*REGBYTES(sp)
- SREG x12, 12*REGBYTES(sp)
- SREG x13, 13*REGBYTES(sp)
- SREG x14, 14*REGBYTES(sp)
- SREG x15, 15*REGBYTES(sp)
- SREG x16, 16*REGBYTES(sp)
- SREG x17, 17*REGBYTES(sp)
- SREG x18, 18*REGBYTES(sp)
- SREG x19, 19*REGBYTES(sp)
- SREG x20, 20*REGBYTES(sp)
- SREG x21, 21*REGBYTES(sp)
- SREG x22, 22*REGBYTES(sp)
- SREG x23, 23*REGBYTES(sp)
- SREG x24, 24*REGBYTES(sp)
- SREG x25, 25*REGBYTES(sp)
- SREG x26, 26*REGBYTES(sp)
- SREG x27, 27*REGBYTES(sp)
- SREG x28, 28*REGBYTES(sp)
- SREG x29, 29*REGBYTES(sp)
- SREG x30, 30*REGBYTES(sp)
- SREG x31, 31*REGBYTES(sp)
- csrr a0, mcause
- csrr a1, mepc
- mv a2, sp
- jal handle_trap
- csrw mepc, a0
-
-/*
- * Remain in M-mode after mret
- */
- li t0, MSTATUS_MPP
- csrs mstatus, t0
- LREG x1, 1*REGBYTES(sp)
- LREG x2, 2*REGBYTES(sp)
- LREG x3, 3*REGBYTES(sp)
- LREG x4, 4*REGBYTES(sp)
- LREG x5, 5*REGBYTES(sp)
- LREG x6, 6*REGBYTES(sp)
- LREG x7, 7*REGBYTES(sp)
- LREG x8, 8*REGBYTES(sp)
- LREG x9, 9*REGBYTES(sp)
- LREG x10, 10*REGBYTES(sp)
- LREG x11, 11*REGBYTES(sp)
- LREG x12, 12*REGBYTES(sp)
- LREG x13, 13*REGBYTES(sp)
- LREG x14, 14*REGBYTES(sp)
- LREG x15, 15*REGBYTES(sp)
- LREG x16, 16*REGBYTES(sp)
- LREG x17, 17*REGBYTES(sp)
- LREG x18, 18*REGBYTES(sp)
- LREG x19, 19*REGBYTES(sp)
- LREG x20, 20*REGBYTES(sp)
- LREG x21, 21*REGBYTES(sp)
- LREG x22, 22*REGBYTES(sp)
- LREG x23, 23*REGBYTES(sp)
- LREG x24, 24*REGBYTES(sp)
- LREG x25, 25*REGBYTES(sp)
- LREG x26, 26*REGBYTES(sp)
- LREG x27, 27*REGBYTES(sp)
- LREG x28, 28*REGBYTES(sp)
- LREG x29, 29*REGBYTES(sp)
- LREG x30, 30*REGBYTES(sp)
- LREG x31, 31*REGBYTES(sp)
- addi sp, sp, 32*REGBYTES
- mret
--
2.7.4
next prev parent reply other threads:[~2018-11-13 8:22 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-13 8:21 [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 01/19] riscv: add Kconfig entries for the code model Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 02/19] dm: cpu: Add timebase frequency to the platdata Bin Meng
2018-11-13 20:01 ` Simon Glass
2018-11-14 1:14 ` Bin Meng
2018-11-15 19:21 ` Simon Glass
2018-11-14 21:17 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 03/19] riscv: qemu: Create a simple-bus driver for the soc node Bin Meng
2018-11-14 21:26 ` Auer, Lukas
2018-11-30 9:47 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 04/19] cpu: Add a RISC-V CPU driver Bin Meng
2018-11-14 21:57 ` Auer, Lukas
2018-12-07 13:59 ` Bin Meng
2018-12-11 0:03 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 05/19] riscv: Add a SYSCON driver for Core Local Interruptor Bin Meng
2018-11-13 14:45 ` Auer, Lukas
2018-11-14 1:48 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A4925E@ATCPCS16.andestech.com>
2018-11-14 8:02 ` Rick Chen
2018-11-14 10:33 ` Auer, Lukas
2018-12-05 9:59 ` Bin Meng
2018-12-05 23:11 ` Auer, Lukas
2018-12-06 10:07 ` Bin Meng
2018-12-06 12:30 ` Auer, Lukas
2018-12-07 14:00 ` Bin Meng
2018-12-06 14:33 ` Philipp Tomsich
2018-12-07 14:01 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 06/19] timer: Add driver for RISC-V privileged architecture defined timer Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 07/19] riscv: kconfig: Allow platform to specify Kconfig options Bin Meng
2018-11-14 22:05 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN Bin Meng
2018-11-14 22:11 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 09/19] riscv: qemu: Probe cpus during boot Bin Meng
2018-11-14 22:21 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 10/19] riscv: Add CSR numbers Bin Meng
2018-11-14 22:26 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 11/19] riscv: Add exception codes for xcause register Bin Meng
2018-11-13 8:22 ` [U-Boot] [PATCH 12/19] riscv: Do some basic architecture level cpu initialization Bin Meng
2018-11-15 23:10 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-12-03 22:22 ` Auer, Lukas
2018-11-13 8:22 ` Bin Meng [this message]
2018-11-14 22:44 ` [U-Boot] [PATCH 13/19] riscv: Move trap handler codes to mtrap.S Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 14/19] riscv: Fix context restore before returning from trap handler Bin Meng
2018-11-14 22:46 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 15/19] riscv: Return to previous privilege level after trap handling Bin Meng
2018-11-14 22:49 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 16/19] riscv: Adjust the _exit_trap() position to come before handle_trap() Bin Meng
2018-11-14 22:50 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 17/19] riscv: Pass correct exception code to _exit_trap() Bin Meng
2018-11-14 22:58 ` Auer, Lukas
2018-11-30 9:56 ` Bin Meng
2018-12-03 22:36 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 18/19] riscv: Refactor handle_trap() a little for future extension Bin Meng
2018-11-14 23:01 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 19/19] riscv: Allow U-Boot to run on hart 0 only Bin Meng
2018-11-14 23:05 ` Auer, Lukas
2018-12-03 7:58 ` [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver Anup Patel
2018-12-03 8:04 ` Bin Meng
2018-12-06 3:37 ` Anup Patel
2018-12-06 8:43 ` Bin Meng
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1542097327-6629-14-git-send-email-bmeng.cn@gmail.com \
--to=bmeng.cn@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox