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From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 01/19] riscv: add Kconfig entries for the code model
Date: Tue, 13 Nov 2018 00:21:49 -0800	[thread overview]
Message-ID: <1542097327-6629-2-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com>

From: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

RISC-V has two code models, medium low (medlow) and medium any (medany).
Medlow limits addressable memory to a single 2 GiB range between the
absolute addresses -2 GiB and +2 GiB. Medany limits addressable memory
to any single 2 GiB address range.

By default, medlow is selected for U-Boot on both 32-bit and 64-bit
systems.

The -mcmodel compiler flag is selected according to the Kconfig
configuration.

Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
[bmeng: adjust to make medlow the default code model for U-Boot]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

---

 arch/riscv/Kconfig  | 18 ++++++++++++++++++
 arch/riscv/Makefile |  9 ++++++++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 0de77a7..a37e895 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -38,6 +38,24 @@ config ARCH_RV64I
 
 endchoice
 
+choice
+	prompt "Code Model"
+	default CMODEL_MEDLOW
+
+config CMODEL_MEDLOW
+	bool "medium low code model"
+	help
+	  U-Boot and its statically defined symbols must lie within a single 2 GiB
+	  address range and must lie between absolute addresses -2 GiB and +2 GiB.
+
+config CMODEL_MEDANY
+	bool "medium any code model"
+	help
+	  U-Boot and its statically defined symbols must be within any single 2 GiB
+	  address range.
+
+endchoice
+
 config RISCV_ISA_C
 	bool "Emit compressed instructions"
 	default y
diff --git a/arch/riscv/Makefile b/arch/riscv/Makefile
index 55d7c65..0b80eb8 100644
--- a/arch/riscv/Makefile
+++ b/arch/riscv/Makefile
@@ -17,8 +17,15 @@ endif
 ifeq ($(CONFIG_RISCV_ISA_C),y)
 	ARCH_C = c
 endif
+ifeq ($(CONFIG_CMODEL_MEDLOW),y)
+	CMODEL = medlow
+endif
+ifeq ($(CONFIG_CMODEL_MEDANY),y)
+	CMODEL = medany
+endif
 
-ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI)
+ARCH_FLAGS = -march=$(ARCH_BASE)$(ARCH_A)$(ARCH_C) -mabi=$(ABI) \
+	     -mcmodel=$(CMODEL)
 
 PLATFORM_CPPFLAGS	+= $(ARCH_FLAGS)
 CFLAGS_EFI		+= $(ARCH_FLAGS)
-- 
2.7.4

  reply	other threads:[~2018-11-13  8:21 UTC|newest]

Thread overview: 62+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-13  8:21 [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver Bin Meng
2018-11-13  8:21 ` Bin Meng [this message]
2018-11-13  8:21 ` [U-Boot] [PATCH 02/19] dm: cpu: Add timebase frequency to the platdata Bin Meng
2018-11-13 20:01   ` Simon Glass
2018-11-14  1:14     ` Bin Meng
2018-11-15 19:21       ` Simon Glass
2018-11-14 21:17   ` Auer, Lukas
2018-11-13  8:21 ` [U-Boot] [PATCH 03/19] riscv: qemu: Create a simple-bus driver for the soc node Bin Meng
2018-11-14 21:26   ` Auer, Lukas
2018-11-30  9:47     ` Bin Meng
2018-11-13  8:21 ` [U-Boot] [PATCH 04/19] cpu: Add a RISC-V CPU driver Bin Meng
2018-11-14 21:57   ` Auer, Lukas
2018-12-07 13:59     ` Bin Meng
2018-12-11  0:03       ` Auer, Lukas
2018-11-13  8:21 ` [U-Boot] [PATCH 05/19] riscv: Add a SYSCON driver for Core Local Interruptor Bin Meng
2018-11-13 14:45   ` Auer, Lukas
2018-11-14  1:48     ` Bin Meng
     [not found]       ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A4925E@ATCPCS16.andestech.com>
2018-11-14  8:02         ` Rick Chen
2018-11-14 10:33       ` Auer, Lukas
2018-12-05  9:59         ` Bin Meng
2018-12-05 23:11           ` Auer, Lukas
2018-12-06 10:07             ` Bin Meng
2018-12-06 12:30               ` Auer, Lukas
2018-12-07 14:00                 ` Bin Meng
2018-12-06 14:33   ` Philipp Tomsich
2018-12-07 14:01     ` Bin Meng
2018-11-13  8:21 ` [U-Boot] [PATCH 06/19] timer: Add driver for RISC-V privileged architecture defined timer Bin Meng
2018-11-13  8:21 ` [U-Boot] [PATCH 07/19] riscv: kconfig: Allow platform to specify Kconfig options Bin Meng
2018-11-14 22:05   ` Auer, Lukas
2018-11-13  8:21 ` [U-Boot] [PATCH 08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN Bin Meng
2018-11-14 22:11   ` Auer, Lukas
2018-11-13  8:21 ` [U-Boot] [PATCH 09/19] riscv: qemu: Probe cpus during boot Bin Meng
2018-11-14 22:21   ` Auer, Lukas
2018-11-30  9:48     ` Bin Meng
2018-11-13  8:21 ` [U-Boot] [PATCH 10/19] riscv: Add CSR numbers Bin Meng
2018-11-14 22:26   ` Auer, Lukas
2018-11-30  9:48     ` Bin Meng
2018-11-13  8:21 ` [U-Boot] [PATCH 11/19] riscv: Add exception codes for xcause register Bin Meng
2018-11-13  8:22 ` [U-Boot] [PATCH 12/19] riscv: Do some basic architecture level cpu initialization Bin Meng
2018-11-15 23:10   ` Auer, Lukas
2018-11-30  9:48     ` Bin Meng
2018-12-03 22:22       ` Auer, Lukas
2018-11-13  8:22 ` [U-Boot] [PATCH 13/19] riscv: Move trap handler codes to mtrap.S Bin Meng
2018-11-14 22:44   ` Auer, Lukas
2018-11-13  8:22 ` [U-Boot] [PATCH 14/19] riscv: Fix context restore before returning from trap handler Bin Meng
2018-11-14 22:46   ` Auer, Lukas
2018-11-13  8:22 ` [U-Boot] [PATCH 15/19] riscv: Return to previous privilege level after trap handling Bin Meng
2018-11-14 22:49   ` Auer, Lukas
2018-11-13  8:22 ` [U-Boot] [PATCH 16/19] riscv: Adjust the _exit_trap() position to come before handle_trap() Bin Meng
2018-11-14 22:50   ` Auer, Lukas
2018-11-13  8:22 ` [U-Boot] [PATCH 17/19] riscv: Pass correct exception code to _exit_trap() Bin Meng
2018-11-14 22:58   ` Auer, Lukas
2018-11-30  9:56     ` Bin Meng
2018-12-03 22:36       ` Auer, Lukas
2018-11-13  8:22 ` [U-Boot] [PATCH 18/19] riscv: Refactor handle_trap() a little for future extension Bin Meng
2018-11-14 23:01   ` Auer, Lukas
2018-11-13  8:22 ` [U-Boot] [PATCH 19/19] riscv: Allow U-Boot to run on hart 0 only Bin Meng
2018-11-14 23:05   ` Auer, Lukas
2018-12-03  7:58 ` [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver Anup Patel
2018-12-03  8:04   ` Bin Meng
2018-12-06  3:37 ` Anup Patel
2018-12-06  8:43   ` Bin Meng

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