From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 04/19] cpu: Add a RISC-V CPU driver
Date: Tue, 13 Nov 2018 00:21:52 -0800 [thread overview]
Message-ID: <1542097327-6629-5-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com>
This adds a driver for RISC-V CPU. Note the driver will bind
a RISC-V timer driver if "timebase-frequency" property is
present in the device tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
drivers/cpu/Kconfig | 6 +++
drivers/cpu/Makefile | 1 +
drivers/cpu/riscv_cpu.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 124 insertions(+)
create mode 100644 drivers/cpu/riscv_cpu.c
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index d405200..3d5729f 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -13,3 +13,9 @@ config CPU_MPC83XX
select CLK_MPC83XX
help
Support CPU cores for SoCs of the MPC83xx series.
+
+config CPU_RISCV
+ bool "Enable RISC-V CPU driver"
+ depends on CPU && RISCV
+ help
+ Support CPU cores for RISC-V architecture.
diff --git a/drivers/cpu/Makefile b/drivers/cpu/Makefile
index 858b037..be0300c 100644
--- a/drivers/cpu/Makefile
+++ b/drivers/cpu/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_CPU) += cpu-uclass.o
obj-$(CONFIG_ARCH_BMIPS) += bmips_cpu.o
obj-$(CONFIG_CPU_MPC83XX) += mpc83xx_cpu.o
+obj-$(CONFIG_CPU_RISCV) += riscv_cpu.o
obj-$(CONFIG_SANDBOX) += cpu_sandbox.o
diff --git a/drivers/cpu/riscv_cpu.c b/drivers/cpu/riscv_cpu.c
new file mode 100644
index 0000000..23917db
--- /dev/null
+++ b/drivers/cpu/riscv_cpu.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+ */
+
+#include <common.h>
+#include <cpu.h>
+#include <dm.h>
+#include <errno.h>
+#include <dm/device-internal.h>
+#include <dm/lists.h>
+
+static int riscv_cpu_get_desc(struct udevice *dev, char *buf, int size)
+{
+ const char *isa;
+
+ isa = dev_read_string(dev, "riscv,isa");
+ if (size < (strlen(isa) + 1))
+ return -ENOSPC;
+
+ strcpy(buf, isa);
+
+ return 0;
+}
+
+static int riscv_cpu_get_info(struct udevice *dev, struct cpu_info *info)
+{
+ const char *mmu;
+
+ dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq);
+
+ mmu = dev_read_string(dev, "mmu-type");
+ if (!mmu)
+ info->features |= BIT(CPU_FEAT_MMU);
+
+ return 0;
+}
+
+static int riscv_cpu_get_count(struct udevice *dev)
+{
+ ofnode node;
+ int num = 0;
+
+ ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
+ const char *device_type;
+
+ device_type = ofnode_read_string(node, "device_type");
+ if (!device_type)
+ continue;
+ if (strcmp(device_type, "cpu") == 0)
+ num++;
+ }
+
+ return num;
+}
+
+static int riscv_cpu_bind(struct udevice *dev)
+{
+ struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ struct driver *drv;
+ struct udevice *timer;
+ int ret;
+
+ /* save the hart id */
+ plat->cpu_id = dev_read_addr(dev);
+
+ /* first examine the property in current cpu node */
+ ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq);
+ /* if not found, then look at the parent /cpus node */
+ if (ret)
+ dev_read_u32(dev->parent, "timebase-frequency",
+ &plat->timebase_freq);
+
+ /*
+ * Bind riscv-timer driver on hart 0
+ *
+ * We only instantiate one timer device which is enough for U-Boot.
+ * Pass the "timebase-frequency" value as the driver data for the
+ * timer device.
+ *
+ * Return value is not checked since it's possible that the timer
+ * driver is not included.
+ */
+ if (!plat->cpu_id && plat->timebase_freq) {
+ drv = lists_driver_lookup_name("riscv_timer");
+ if (!drv) {
+ debug("Cannot find the timer driver, not included?\n");
+ return 0;
+ }
+
+ device_bind_with_driver_data(dev, drv, "riscv_timer",
+ plat->timebase_freq, ofnode_null(),
+ &timer);
+ }
+
+ return 0;
+}
+
+static const struct cpu_ops riscv_cpu_ops = {
+ .get_desc = riscv_cpu_get_desc,
+ .get_info = riscv_cpu_get_info,
+ .get_count = riscv_cpu_get_count,
+};
+
+static const struct udevice_id riscv_cpu_ids[] = {
+ { .compatible = "riscv" },
+ { }
+};
+
+U_BOOT_DRIVER(riscv_cpu) = {
+ .name = "riscv_cpu",
+ .id = UCLASS_CPU,
+ .of_match = riscv_cpu_ids,
+ .bind = riscv_cpu_bind,
+ .ops = &riscv_cpu_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.7.4
next prev parent reply other threads:[~2018-11-13 8:21 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-13 8:21 [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 01/19] riscv: add Kconfig entries for the code model Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 02/19] dm: cpu: Add timebase frequency to the platdata Bin Meng
2018-11-13 20:01 ` Simon Glass
2018-11-14 1:14 ` Bin Meng
2018-11-15 19:21 ` Simon Glass
2018-11-14 21:17 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 03/19] riscv: qemu: Create a simple-bus driver for the soc node Bin Meng
2018-11-14 21:26 ` Auer, Lukas
2018-11-30 9:47 ` Bin Meng
2018-11-13 8:21 ` Bin Meng [this message]
2018-11-14 21:57 ` [U-Boot] [PATCH 04/19] cpu: Add a RISC-V CPU driver Auer, Lukas
2018-12-07 13:59 ` Bin Meng
2018-12-11 0:03 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 05/19] riscv: Add a SYSCON driver for Core Local Interruptor Bin Meng
2018-11-13 14:45 ` Auer, Lukas
2018-11-14 1:48 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A4925E@ATCPCS16.andestech.com>
2018-11-14 8:02 ` Rick Chen
2018-11-14 10:33 ` Auer, Lukas
2018-12-05 9:59 ` Bin Meng
2018-12-05 23:11 ` Auer, Lukas
2018-12-06 10:07 ` Bin Meng
2018-12-06 12:30 ` Auer, Lukas
2018-12-07 14:00 ` Bin Meng
2018-12-06 14:33 ` Philipp Tomsich
2018-12-07 14:01 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 06/19] timer: Add driver for RISC-V privileged architecture defined timer Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 07/19] riscv: kconfig: Allow platform to specify Kconfig options Bin Meng
2018-11-14 22:05 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN Bin Meng
2018-11-14 22:11 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 09/19] riscv: qemu: Probe cpus during boot Bin Meng
2018-11-14 22:21 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 10/19] riscv: Add CSR numbers Bin Meng
2018-11-14 22:26 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 11/19] riscv: Add exception codes for xcause register Bin Meng
2018-11-13 8:22 ` [U-Boot] [PATCH 12/19] riscv: Do some basic architecture level cpu initialization Bin Meng
2018-11-15 23:10 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-12-03 22:22 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 13/19] riscv: Move trap handler codes to mtrap.S Bin Meng
2018-11-14 22:44 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 14/19] riscv: Fix context restore before returning from trap handler Bin Meng
2018-11-14 22:46 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 15/19] riscv: Return to previous privilege level after trap handling Bin Meng
2018-11-14 22:49 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 16/19] riscv: Adjust the _exit_trap() position to come before handle_trap() Bin Meng
2018-11-14 22:50 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 17/19] riscv: Pass correct exception code to _exit_trap() Bin Meng
2018-11-14 22:58 ` Auer, Lukas
2018-11-30 9:56 ` Bin Meng
2018-12-03 22:36 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 18/19] riscv: Refactor handle_trap() a little for future extension Bin Meng
2018-11-14 23:01 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 19/19] riscv: Allow U-Boot to run on hart 0 only Bin Meng
2018-11-14 23:05 ` Auer, Lukas
2018-12-03 7:58 ` [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver Anup Patel
2018-12-03 8:04 ` Bin Meng
2018-12-06 3:37 ` Anup Patel
2018-12-06 8:43 ` Bin Meng
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