From: Bin Meng <bmeng.cn@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 07/19] riscv: kconfig: Allow platform to specify Kconfig options
Date: Tue, 13 Nov 2018 00:21:55 -0800 [thread overview]
Message-ID: <1542097327-6629-8-git-send-email-bmeng.cn@gmail.com> (raw)
In-Reply-To: <1542097327-6629-1-git-send-email-bmeng.cn@gmail.com>
At present there are just two levels of Kconfig option hierarchy in
RISC-V. This adds a new level for platform to specify additional
options. It is organized in a way that platform-specific options
followed by board-specific ones, so that when it comes to the same
Kconfig option, board-specific one takes take the highest precedence,
then platform-specific one, and finally architecture-specific one.
As an example, add the QEMU RISC-V platform-specific Kconfig options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---
arch/riscv/Kconfig | 6 ++++++
arch/riscv/cpu/qemu/Kconfig | 9 +++++++++
board/emulation/qemu-riscv/Kconfig | 1 +
3 files changed, 16 insertions(+)
create mode 100644 arch/riscv/cpu/qemu/Kconfig
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index abfc083..4292ffd 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -16,9 +16,15 @@ config TARGET_QEMU_VIRT
endchoice
+# board-specific options below
source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
+# platform-specific options below
+source "arch/riscv/cpu/qemu/Kconfig"
+
+# architecture-specific options below
+
choice
prompt "Base ISA"
default ARCH_RV32I
diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/qemu/Kconfig
new file mode 100644
index 0000000..ec5d934
--- /dev/null
+++ b/arch/riscv/cpu/qemu/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
+
+config QEMU_RISCV
+ bool
+ imply CPU
+ imply CPU_RISCV
+ imply RISCV_TIMER
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 33ca253..bfe050c 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -17,6 +17,7 @@ config SYS_TEXT_BASE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
+ select QEMU_RISCV
imply SYS_NS16550
imply VIRTIO_MMIO
imply VIRTIO_NET
--
2.7.4
next prev parent reply other threads:[~2018-11-13 8:21 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-13 8:21 [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 01/19] riscv: add Kconfig entries for the code model Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 02/19] dm: cpu: Add timebase frequency to the platdata Bin Meng
2018-11-13 20:01 ` Simon Glass
2018-11-14 1:14 ` Bin Meng
2018-11-15 19:21 ` Simon Glass
2018-11-14 21:17 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 03/19] riscv: qemu: Create a simple-bus driver for the soc node Bin Meng
2018-11-14 21:26 ` Auer, Lukas
2018-11-30 9:47 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 04/19] cpu: Add a RISC-V CPU driver Bin Meng
2018-11-14 21:57 ` Auer, Lukas
2018-12-07 13:59 ` Bin Meng
2018-12-11 0:03 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 05/19] riscv: Add a SYSCON driver for Core Local Interruptor Bin Meng
2018-11-13 14:45 ` Auer, Lukas
2018-11-14 1:48 ` Bin Meng
[not found] ` <752D002CFF5D0F4FA35C0100F1D73F3FA3A4925E@ATCPCS16.andestech.com>
2018-11-14 8:02 ` Rick Chen
2018-11-14 10:33 ` Auer, Lukas
2018-12-05 9:59 ` Bin Meng
2018-12-05 23:11 ` Auer, Lukas
2018-12-06 10:07 ` Bin Meng
2018-12-06 12:30 ` Auer, Lukas
2018-12-07 14:00 ` Bin Meng
2018-12-06 14:33 ` Philipp Tomsich
2018-12-07 14:01 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 06/19] timer: Add driver for RISC-V privileged architecture defined timer Bin Meng
2018-11-13 8:21 ` Bin Meng [this message]
2018-11-14 22:05 ` [U-Boot] [PATCH 07/19] riscv: kconfig: Allow platform to specify Kconfig options Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 08/19] riscv: Enlarge the default SYS_MALLOC_F_LEN Bin Meng
2018-11-14 22:11 ` Auer, Lukas
2018-11-13 8:21 ` [U-Boot] [PATCH 09/19] riscv: qemu: Probe cpus during boot Bin Meng
2018-11-14 22:21 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 10/19] riscv: Add CSR numbers Bin Meng
2018-11-14 22:26 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-11-13 8:21 ` [U-Boot] [PATCH 11/19] riscv: Add exception codes for xcause register Bin Meng
2018-11-13 8:22 ` [U-Boot] [PATCH 12/19] riscv: Do some basic architecture level cpu initialization Bin Meng
2018-11-15 23:10 ` Auer, Lukas
2018-11-30 9:48 ` Bin Meng
2018-12-03 22:22 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 13/19] riscv: Move trap handler codes to mtrap.S Bin Meng
2018-11-14 22:44 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 14/19] riscv: Fix context restore before returning from trap handler Bin Meng
2018-11-14 22:46 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 15/19] riscv: Return to previous privilege level after trap handling Bin Meng
2018-11-14 22:49 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 16/19] riscv: Adjust the _exit_trap() position to come before handle_trap() Bin Meng
2018-11-14 22:50 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 17/19] riscv: Pass correct exception code to _exit_trap() Bin Meng
2018-11-14 22:58 ` Auer, Lukas
2018-11-30 9:56 ` Bin Meng
2018-12-03 22:36 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 18/19] riscv: Refactor handle_trap() a little for future extension Bin Meng
2018-11-14 23:01 ` Auer, Lukas
2018-11-13 8:22 ` [U-Boot] [PATCH 19/19] riscv: Allow U-Boot to run on hart 0 only Bin Meng
2018-11-14 23:05 ` Auer, Lukas
2018-12-03 7:58 ` [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver Anup Patel
2018-12-03 8:04 ` Bin Meng
2018-12-06 3:37 ` Anup Patel
2018-12-06 8:43 ` Bin Meng
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