[U-Boot] [PATCH 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

[tien.fong.chee at intel.com <tien.fong.chee@intel.com>]

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
 .../fpga/altera-socfpga-a10-fpga-mgr.txt           |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a..010322a 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,6 +7,10 @@ Required properties:
                - The second index is for writing FPGA configuration data.
 - resets     : Phandle and reset specifier for the device's reset.
 - clocks     : Clocks used by the device.
+- altr,bitstream_periph : File name for FPGA peripheral raw binary which is used
+			  to initialize FPGA IOs, PLL, IO48 and DDR.
+- altr,bitstream_core : File name for core raw binary which contains FPGA design
+			which is used to program FPGA CRAM and ERAM.
 
 Example:
 
@@ -16,4 +20,6 @@ Example:
 		       0xffcfe400 0x20>;
 		clocks = <&l4_mp_clk>;
 		resets = <&rst FPGAMGR_RESET>;
+		altr,bitstream_periph = "ghrd_10as066n2.periph.rbf.mkimage";
+		altr,bitstream_core = "ghrd_10as066n2.core.rbf.mkimage";
 	};
-- 
1.7.7.4