From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chee, Tien Fong Date: Fri, 23 Nov 2018 09:19:24 +0000 Subject: [U-Boot] [PATCH 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 In-Reply-To: <4634432b-366f-a1ad-10ab-708d7ee95f3b@denx.de> References: <1542796908-7947-1-git-send-email-tien.fong.chee@intel.com> <1542796908-7947-2-git-send-email-tien.fong.chee@intel.com> <4634432b-366f-a1ad-10ab-708d7ee95f3b@denx.de> Message-ID: <1542964763.10129.5.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Wed, 2018-11-21 at 15:11 +0100, Marek Vasut wrote: > On 11/21/2018 11:41 AM, tien.fong.chee at intel.com wrote: > > > > From: Tien Fong Chee > > > > This patch adds description on properties about file name used for > > both > > peripheral bitstream and core bitstream. > > > > Signed-off-by: Tien Fong Chee > > --- > >  .../fpga/altera-socfpga-a10-fpga-mgr.txt           |    6 ++++++ > >  1 files changed, 6 insertions(+), 0 deletions(-) > > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga- > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga- > > mgr.txt > > index 2fd8e7a..010322a 100644 > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt > > @@ -7,6 +7,10 @@ Required properties: > >                 - The second index is for writing FPGA > > configuration data. > >  - resets     : Phandle and reset specifier for the device's reset. > >  - clocks     : Clocks used by the device. > > +- altr,bitstream_periph : File name for FPGA peripheral raw binary > > which is used > > +   to initialize FPGA IOs, PLL, IO48 and > > DDR. > > +- altr,bitstream_core : File name for core raw binary which > > contains FPGA design > > + which is used to program FPGA CRAM and > > ERAM. > bitstream- instead of bitstream_ Noted. > > btw can we get something that works with full bitstream too ? This patchset actually support the full bitstream too, unfortunately it is blocked by hardware MPFE issue. The patchset for the MPFE workaround would come after this patchset. I would advice to use the early IO release method for the sake of performance. For details of issue, you can read the from the link https://github.com /altera-opensource/u-boot-socfpga/commits/socfpga_v2014.10_arria10_brin gup FogBugz #410989-6: Masking hardware sequenced warm reset for logic in…  … Tien Fong Chee Tien Fong Chee committed on Feb 16, 2017   FogBugz #410989-5: Enable RAM boot  … Tien Fong Chee Tien Fong Chee committed on Feb 16, 2017   FogBugz #410989-4: Added software reset for QSPI  … Tien Fong Chee Tien Fong Chee committed on Feb 8, 2017   FogBugz #410989-3: Disable redundant redundant messages after a warm …  … Tien Fong Chee Tien Fong Chee committed on Dec 21, 2016   FogBugz #410989-2: Reset MPFE NoC after programming periperal rbf  … Tien Fong Chee Tien Fong Chee committed on Dec 21, 2016   FogBugz #410989-1: Functions for setting/checking magic no. to isw_ha…  … Tien Fong Chee Tien Fong Chee committed on Dec 21, 2016 > > > > >  Example: > >   > > @@ -16,4 +20,6 @@ Example: > >          0xffcfe400 0x20>; > >   clocks = <&l4_mp_clk>; > >   resets = <&rst FPGAMGR_RESET>; > > + altr,bitstream_periph = > > "ghrd_10as066n2.periph.rbf.mkimage"; > > + altr,bitstream_core = > > "ghrd_10as066n2.core.rbf.mkimage"; > >   }; > > >