[U-Boot] [PATCH 8/9] ARM: socfpga: Add default fitImage for Arria10 SoCDK

tien.fong.chee at intel.com
2018-11-21T10:41:47Z

From: Tien Fong Chee <tien.fong.chee@intel.com>

Add default fitImage file bundling U-Boot and FPGA bitstream for Arria10.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
---
board/altera/arria10-socdk/fit_spl_fpga.its | 54 +++++++++++++++++++++++++++
1 files changed, 54 insertions(+), 0 deletions(-)
create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its

diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its b/board/altera/arria10-socdk/fit_spl_fpga.its
new file mode 100644
index 0000000..7782740
--- /dev/null
+++ b/board/altera/arria10-socdk/fit_spl_fpga.its
@@ -0,0 +1,54 @@
+/*
+ * The fitImage source for Arria 10 SoCDK loading FPGA bitstream and U-Boot
+ *
+ * Copyright (C) 2018 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+
+/ {
+ description = "FIT image with U-Boot proper and FPGA bitstream";
+ #address-cells = <1>;
+
+ images {
+ uboot {
+ description = "U-Boot (32-bit)";
+ data = /incbin/("../../../u-boot-nodtb.bin");
+ type = "standalone";
+ os = "U-Boot";
+ arch = "arm";
+ compression = "none";
+ load = <0x01000040>;
+ entry = <0x01000040>;
+ };
+
+ fdt {
+ description = "Arria10 SoCDK flat device-tree";
+ data = /incbin/("../../../u-boot.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ load = <0x00f00000>;
+ };
+
+ fpga {
+ description = "FPGA bitstream";
+ data = /incbin/("../../../ghrd_10as066n2.core.rbf");
+ type = "fpga";
+ compression = "none";
+ load = <0x1000>;
+ };
+ };
+
+ configurations {
+ default = "conf";
+ conf {
+ description = "Altera Arria10 SoCDK";
+ loadables = "uboot";
+ fdt = "fdt";
+ fpga = "fpga";
+ };
+ };
+};
--
1.7.7.4