From: chee.hong.ang at intel.com <chee.hong.ang@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v5 3/4] arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table
Date: Thu, 29 Nov 2018 01:40:14 -0800 [thread overview]
Message-ID: <1543484415-26499-4-git-send-email-chee.hong.ang@intel.com> (raw)
In-Reply-To: <1543484415-26499-1-git-send-email-chee.hong.ang@intel.com>
From: "Ang, Chee Hong" <chee.hong.ang@intel.com>
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
---
arch/arm/mach-socfpga/Makefile | 4 ++
arch/arm/mach-socfpga/fpga_device.c | 59 ++++++++++++++++++++++++
arch/arm/mach-socfpga/include/mach/fpga_device.h | 15 ++++++
arch/arm/mach-socfpga/include/mach/misc.h | 6 ---
arch/arm/mach-socfpga/misc.c | 31 -------------
arch/arm/mach-socfpga/misc_arria10.c | 1 +
arch/arm/mach-socfpga/misc_gen5.c | 1 +
arch/arm/mach-socfpga/misc_s10.c | 3 ++
drivers/fpga/altera.c | 6 +++
include/altera.h | 4 ++
10 files changed, 93 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/mach-socfpga/fpga_device.c
create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_device.h
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index e667204..2ff1b3f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -10,6 +10,10 @@ obj-y += clock_manager.o
obj-y += misc.o
obj-y += reset_manager.o
+ifdef CONFIG_FPGA
+obj-y += fpga_device.o
+endif
+
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += clock_manager_gen5.o
obj-y += misc_gen5.o
diff --git a/arch/arm/mach-socfpga/fpga_device.c b/arch/arm/mach-socfpga/fpga_device.c
new file mode 100644
index 0000000..97b27eb
--- /dev/null
+++ b/arch/arm/mach-socfpga/fpga_device.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ */
+
+#include <common.h>
+#include <altera.h>
+
+#ifdef CONFIG_FPGA_STRATIX10
+/*
+ * FPGA programming support for SoC FPGA Stratix 10
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Intel_FPGA_Stratix10,
+ /* Interface type */
+ secure_device_manager_mailbox,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
+};
+#else
+/*
+ * FPGA programming support for SoC FPGA Cyclone V
+ */
+static Altera_desc altera_fpga[] = {
+ {
+ /* Family */
+ Altera_SoCFPGA,
+ /* Interface type */
+ fast_passive_parallel,
+ /* No limitation as additional data will be ignored */
+ -1,
+ /* No device function table */
+ NULL,
+ /* Base interface address specified in driver */
+ NULL,
+ /* No cookie implementation */
+ 0
+ },
+};
+#endif
+
+/* add device descriptor to FPGA device table */
+void socfpga_fpga_add(void)
+{
+ int i;
+
+ fpga_init();
+ for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
+ fpga_add(fpga_altera, &altera_fpga[i]);
+}
diff --git a/arch/arm/mach-socfpga/include/mach/fpga_device.h b/arch/arm/mach-socfpga/include/mach/fpga_device.h
new file mode 100644
index 0000000..fc80cbd
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/fpga_device.h
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _FPGA_DEVICE_H_
+#define _FPGA_DEVICE_H_
+
+#ifdef CONFIG_FPGA
+void socfpga_fpga_add(void);
+#else
+inline void socfpga_fpga_add(void) {}
+#endif
+
+#endif /* _FPGA_DEVICE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h
index 4fc9570..cb0eb3b 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -15,12 +15,6 @@ struct bsel {
extern struct bsel bsel_str[];
-#ifdef CONFIG_FPGA
-void socfpga_fpga_add(void);
-#else
-static inline void socfpga_fpga_add(void) {}
-#endif
-
#ifdef CONFIG_TARGET_SOCFPGA_GEN5
void socfpga_sdram_remap_zero(void);
#endif
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index a4f6d5c..f493da0 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -87,37 +87,6 @@ int overwrite_console(void)
}
#endif
-#ifdef CONFIG_FPGA
-/*
- * FPGA programming support for SoC FPGA Cyclone V
- */
-static Altera_desc altera_fpga[] = {
- {
- /* Family */
- Altera_SoCFPGA,
- /* Interface type */
- fast_passive_parallel,
- /* No limitation as additional data will be ignored */
- -1,
- /* No device function table */
- NULL,
- /* Base interface address specified in driver */
- NULL,
- /* No cookie implementation */
- 0
- },
-};
-
-/* add device descriptor to FPGA device table */
-void socfpga_fpga_add(void)
-{
- int i;
- fpga_init();
- for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
- fpga_add(fpga_altera, &altera_fpga[i]);
-}
-#endif
-
int arch_cpu_init(void)
{
#ifdef CONFIG_HW_WATCHDOG
diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c
index f347ae8..6c4eb31 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -17,6 +17,7 @@
#include <asm/arch/reset_manager_arria10.h>
#include <asm/arch/sdram_arria10.h>
#include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_device.h>
#include <asm/arch/nic301.h>
#include <asm/io.h>
#include <asm/pl310.h>
diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c
index 429c3d6..9e0eeb7 100644
--- a/arch/arm/mach-socfpga/misc_gen5.c
+++ b/arch/arm/mach-socfpga/misc_gen5.c
@@ -17,6 +17,7 @@
#include <asm/arch/scan_manager.h>
#include <asm/arch/sdram.h>
#include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_device.h>
#include <asm/arch/nic301.h>
#include <asm/arch/scu.h>
#include <asm/pl310.h>
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c
index e599362..fce9077 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_s10.c
@@ -13,6 +13,7 @@
#include <asm/io.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/system_manager.h>
+#include <asm/arch/fpga_device.h>
#include <asm/arch/misc.h>
#include <asm/pl310.h>
#include <linux/libfdt.h>
@@ -125,6 +126,8 @@ int arch_misc_init(void)
int arch_early_init_r(void)
{
+ socfpga_fpga_add();
+
return 0;
}
diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c
index 9605554..7c8f518 100644
--- a/drivers/fpga/altera.c
+++ b/drivers/fpga/altera.c
@@ -39,6 +39,9 @@ static const struct altera_fpga {
#if defined(CONFIG_FPGA_STRATIX_V)
{ Altera_StratixV, "StratixV", stratixv_load, NULL, NULL },
#endif
+#if defined(CONFIG_FPGA_STRATIX10)
+ { Intel_FPGA_Stratix10, "Stratix10", stratix10_load, NULL, NULL },
+#endif
#if defined(CONFIG_FPGA_SOCFPGA)
{ Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL },
#endif
@@ -154,6 +157,9 @@ int altera_info(Altera_desc *desc)
case fast_passive_parallel_security:
printf("Fast Passive Parallel with Security (FPPS)\n");
break;
+ case secure_device_manager_mailbox:
+ puts("Secure Device Manager (SDM) Mailbox\n");
+ break;
/* Add new interface types here */
default:
printf("Unsupported interface type, %d\n", desc->iface);
diff --git a/include/altera.h b/include/altera.h
index 233b467..22d55cf 100644
--- a/include/altera.h
+++ b/include/altera.h
@@ -39,6 +39,8 @@ enum altera_iface {
fast_passive_parallel,
/* fast passive parallel with security (FPPS) */
fast_passive_parallel_security,
+ /* secure device manager (SDM) mailbox */
+ secure_device_manager_mailbox,
/* insert all new types before this */
max_altera_iface_type,
};
@@ -54,6 +56,8 @@ enum altera_family {
Altera_StratixII,
/* StratixV Family */
Altera_StratixV,
+ /* Stratix10 Family */
+ Intel_FPGA_Stratix10,
/* SoCFPGA Family */
Altera_SoCFPGA,
--
2.7.4
next prev parent reply other threads:[~2018-11-29 9:40 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-29 9:40 [U-Boot] [PATCH v5 0/4] Stratix10 FPGA reconfiguration support chee.hong.ang at intel.com
2018-11-29 9:40 ` [U-Boot] [PATCH v5 1/4] arm: socfpga: stratix10: Add macros for mailbox's arguments chee.hong.ang at intel.com
2018-11-29 9:40 ` [U-Boot] [PATCH v5 2/4] arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver chee.hong.ang at intel.com
2018-11-29 9:40 ` chee.hong.ang at intel.com [this message]
2018-11-29 11:28 ` [U-Boot] [PATCH v5 3/4] arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table Marek Vasut
2018-12-17 6:38 ` Ang, Chee Hong
2018-12-17 13:04 ` Marek Vasut
2018-11-29 9:40 ` [U-Boot] [PATCH v5 4/4] arm: socfpga: stratix10: Enable Stratix10 FPGA Reconfiguration chee.hong.ang at intel.com
2018-11-29 11:25 ` [U-Boot] [PATCH v5 0/4] Stratix10 FPGA reconfiguration support Marek Vasut
2018-12-17 6:36 ` Ang, Chee Hong
2018-12-17 13:12 ` Marek Vasut
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