From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chee, Tien Fong Date: Tue, 1 Jan 2019 03:32:35 +0000 Subject: [U-Boot] [PATCH 3/6] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK In-Reply-To: <796e0794-4be9-bfcc-82b2-a994e57c7661@denx.de> References: <1546157627-45489-1-git-send-email-tien.fong.chee@intel.com> <1546157627-45489-4-git-send-email-tien.fong.chee@intel.com> <796e0794-4be9-bfcc-82b2-a994e57c7661@denx.de> Message-ID: <1546313555.10462.29.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Sun, 2018-12-30 at 16:47 +0100, Marek Vasut wrote: > On 12/30/18 9:13 AM, tien.fong.chee at intel.com wrote: > > > > From: Tien Fong Chee > > > > Update the default configuration file to enable the necessary > > functionality > > to get the SoCFPGA loadfs driver support. This would enable the > > implementation of programming bitstream into FPGA from MMC. > > > > Signed-off-by: Tien Fong Chee > > --- > >  configs/socfpga_arria10_defconfig |    8 ++++++++ > >  1 files changed, 8 insertions(+), 0 deletions(-) > > > > diff --git a/configs/socfpga_arria10_defconfig > > b/configs/socfpga_arria10_defconfig > > index 6ebda81..8158dbb 100644 > > --- a/configs/socfpga_arria10_defconfig > > +++ b/configs/socfpga_arria10_defconfig > > @@ -27,8 +27,16 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" > >  # CONFIG_EFI_PARTITION is not set > >  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" > >  CONFIG_ENV_IS_IN_MMC=y > > +CONFIG_SPL_ENV_SUPPORT=y > >  CONFIG_SPL_DM=y > >  CONFIG_SPL_DM_SEQ_ALIAS=y > > +CONFIG_SPL_DM_MMC=y > > +CONFIG_SPL_MMC_SUPPORT=y > > +CONFIG_SPL_EXT_SUPPORT=y > > +CONFIG_SPL_FAT_SUPPORT=y > > +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y > > +CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 > This breaks systems with large FAT clusters. Why is this needed for > programming the FPGA from MMC ? This is final tuning in term of getting balance between performance and SPL image size for the socdk devkit. User can change that if they need large FAT cluster in their design, right? > > > > > +CONFIG_FS_LOADER=y > >  CONFIG_FPGA_SOCFPGA=y > >  CONFIG_DM_GPIO=y > >  CONFIG_DWAPB_GPIO=y > > >