From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chee, Tien Fong Date: Tue, 1 Jan 2019 03:39:11 +0000 Subject: [U-Boot] [PATCH 5/6] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs In-Reply-To: <1d8a83e1-14c8-cd36-0f3b-59ceffe38fe3@denx.de> References: <1546157627-45489-1-git-send-email-tien.fong.chee@intel.com> <1546157627-45489-6-git-send-email-tien.fong.chee@intel.com> <1d8a83e1-14c8-cd36-0f3b-59ceffe38fe3@denx.de> Message-ID: <1546313950.10462.32.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Sun, 2018-12-30 at 16:51 +0100, Marek Vasut wrote: > On 12/30/18 9:13 AM, tien.fong.chee at intel.com wrote: > > > > From: Tien Fong Chee > > > > Add support for loading FPGA bitstream to get DDR up running before > > U-Boot is loaded into DDR. Boot device initialization, generic > > firmware > > loader and SPL FAT support are required for this whole mechanism to > > work. > > > > Signed-off-by: Tien Fong Chee > > --- > >  arch/arm/mach-socfpga/spl_a10.c |   46 > > ++++++++++++++++++++++++++++++++++++++- > >  1 files changed, 45 insertions(+), 1 deletions(-) > > > > diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach- > > socfpga/spl_a10.c > > index 3ea64f7..93f5f46 100644 > > --- a/arch/arm/mach-socfpga/spl_a10.c > > +++ b/arch/arm/mach-socfpga/spl_a10.c > > @@ -1,6 +1,6 @@ > >  // SPDX-License-Identifier: GPL-2.0+ > >  /* > > - *  Copyright (C) 2012 Altera Corporation > > + *  Copyright (C) 2012-2018 Altera Corporation > >   */ > >   > >  #include > > @@ -23,9 +23,14 @@ > >  #include > >  #include > >  #include > > +#include > > +#include > >   > >  DECLARE_GLOBAL_DATA_PTR; > >   > > +#define FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR (1 * 1024) > > +#define FPGA_SOCFGA_A10_RBF_CORE_BUFFER_SIZE (40 * 1024 * > > 1024) > > + > >  static const struct socfpga_system_manager *sysmgr_regs = > >   (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; > >   > > @@ -73,6 +78,45 @@ void spl_board_init(void) > >   WATCHDOG_RESET(); > >   > >   arch_early_init_r(); > > + > > + /* If the full FPGA is already loaded, ie.from EPCQ, > > config fpga pins */ > > + if (is_fpgamgr_user_mode()) { > > + config_pins(gd->fdt_blob, "shared"); > > + config_pins(gd->fdt_blob, "fpga"); > What happens if config_pins() fails ? The function returns some > return > value. There is return value for config_pins, i can add the debug print out for the return value. > > > > > + } else if (!is_fpgamgr_early_user_mode()) { > > + /* Program IOSSM(early IO release) or full FPGA */ > > + fpga_fs_info fpga_fsinfo; > > + int len; > > + char buf[16 * 1024] __aligned(ARCH_DMA_MINALIGN); > > + > > + fpga_fsinfo.filename = (char *)get_fpga_filename( > Is the cast needed ? there is a warning  arch/arm/mach-socfpga/spl_a10.c:109:24: warning: assignment discards 'const' qualifier from pointer target type [-Wdiscarded-qualifiers]    fpga_fsinfo.filename = get_fpga_filename( > > > > > + gd->fdt_blob, > > + &len, > > + FPGA_SOCFPGA_A10_R > > BF_PERIPH); > > + > > + if (fpga_fsinfo.filename) > > + socfpga_loadfs(&fpga_fsinfo, buf, > > sizeof(buf), 0); > > + } > > + > > + /* If the IOSSM/full FPGA is already loaded, start DDR */ > > + if (is_fpgamgr_early_user_mode() || > > is_fpgamgr_user_mode()) > > + ddr_calibration_sequence(); > > + > > + if (!is_fpgamgr_user_mode()) { > > + fpga_fs_info fpga_fsinfo; > > + int len; > > + > > + fpga_fsinfo.filename = (char *)get_fpga_filename( > > + gd->fdt_blob, > > + &len, > > + FPGA_SOCFPGA_A10_R > > BF_CORE); > > + > > + if (fpga_fsinfo.filename) > > + socfpga_loadfs(&fpga_fsinfo, > > + (const void > > *)FPGA_SOCFGA_A10_RBF_CORE_LOAD_DDR, > > + (size_t)FPGA_SOCFGA_A10_RBF_CORE_B > > UFFER_SIZE, > > + 0); > > + } > >  } > >   > >  void board_init_f(ulong dummy) > > >