public inbox for u-boot@lists.denx.de
 help / color / mirror / Atom feed
From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 6/6] ARM: socfpga: Synchronize the configuration for A10 SoCDK
Date: Tue, 1 Jan 2019 03:51:44 +0000	[thread overview]
Message-ID: <1546314704.10462.35.camel@intel.com> (raw)
In-Reply-To: <dae3532d-380c-fb4b-b27c-e4eb7d166a16@denx.de>

On Sun, 2018-12-30 at 16:54 +0100, Marek Vasut wrote:
> On 12/30/18 9:13 AM, tien.fong.chee at intel.com wrote:
> > 
> > From: Marek Vasut <marex@denx.de>
> > 
> > Update the default configuration file to enable the necessary
> > functionality
> > the get the kit working. That includes SPL SD/MMC support, USB, and
> > I2C.
> > 
> > Signed-off-by: Marek Vasut <marex@denx.de>
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> Is this patch needed ? Why ? This enables a whole lot of stuff ....
These settings are mostly syn up from gen5 and our own downstream A10.
These settings are mostly required to boot U-Boot and supporting A10
golden system reference design.
> > 
> > ---
> >  configs/socfpga_arria10_defconfig |   38
> > +++++++++++++++++++++++++++++++-----
> >  1 files changed, 32 insertions(+), 6 deletions(-)
> > 
> > diff --git a/configs/socfpga_arria10_defconfig
> > b/configs/socfpga_arria10_defconfig
> > index 8158dbb..4b93321 100644
> > --- a/configs/socfpga_arria10_defconfig
> > +++ b/configs/socfpga_arria10_defconfig
> > @@ -1,7 +1,7 @@
> >  CONFIG_ARM=y
> >  CONFIG_ARCH_SOCFPGA=y
> >  CONFIG_SYS_TEXT_BASE=0x01000040
> > -CONFIG_SYS_MALLOC_F_LEN=0x2000
> > +CONFIG_SYS_MALLOC_F_LEN=0x8000
> >  CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
> >  CONFIG_SPL=y
> >  CONFIG_IDENT_STRING="socfpga_arria10"
> > @@ -10,26 +10,35 @@ CONFIG_NR_DRAM_BANKS=1
> >  CONFIG_USE_BOOTARGS=y
> >  CONFIG_BOOTARGS="console=ttyS0,115200"
> >  # CONFIG_USE_BOOTCOMMAND is not set
> > +CONFIG_SYS_CONSOLE_IS_IN_ENV=y
> > +CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
> > +CONFIG_SYS_CONSOLE_ENV_OVERWRITE=y
> >  CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
> > +CONFIG_VERSION_VARIABLE=y
> >  CONFIG_DISPLAY_BOARDINFO_LATE=y
> > +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
> >  CONFIG_SPL_FPGA_SUPPORT=y
> > -CONFIG_SPL_SPI_LOAD=y
> >  CONFIG_CMD_ASKENV=y
> >  CONFIG_CMD_GREPENV=y
> > +CONFIG_CMD_DFU=y
> >  # CONFIG_CMD_FLASH is not set
> >  CONFIG_CMD_GPIO=y
> > +CONFIG_CMD_I2C=y
> >  CONFIG_CMD_MMC=y
> > +CONFIG_CMD_SF=y
> > +CONFIG_CMD_SPI=y
> > +CONFIG_CMD_USB=y
> > +CONFIG_CMD_USB_MASS_STORAGE=y
> >  CONFIG_CMD_CACHE=y
> >  CONFIG_CMD_EXT4_WRITE=y
> >  CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
> > -# CONFIG_SPL_DOS_PARTITION is not set
> > -# CONFIG_ISO_PARTITION is not set
> > -# CONFIG_EFI_PARTITION is not set
> > +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-
> > names"
> >  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> >  CONFIG_ENV_IS_IN_MMC=y
> >  CONFIG_SPL_ENV_SUPPORT=y
> >  CONFIG_SPL_DM=y
> >  CONFIG_SPL_DM_SEQ_ALIAS=y
> > +CONFIG_DFU_MMC=y
> >  CONFIG_SPL_DM_MMC=y
> >  CONFIG_SPL_MMC_SUPPORT=y
> >  CONFIG_SPL_EXT_SUPPORT=y
> > @@ -40,13 +49,30 @@ CONFIG_FS_LOADER=y
> >  CONFIG_FPGA_SOCFPGA=y
> >  CONFIG_DM_GPIO=y
> >  CONFIG_DWAPB_GPIO=y
> > +CONFIG_SYS_I2C_DW=y
> >  CONFIG_DM_MMC=y
> >  CONFIG_MTD_DEVICE=y
> > +CONFIG_MTD_PARTITIONS=y
> > +CONFIG_MMC_DW=y
> > +CONFIG_SPI_FLASH=y
> > +CONFIG_SPI_FLASH_BAR=y
> > +CONFIG_SPI_FLASH_SPANSION=y
> > +CONFIG_SPI_FLASH_STMICRO=y
> > +CONFIG_PHY_MICREL=y
> > +CONFIG_PHY_MICREL_KSZ90X1=y
> >  CONFIG_DM_ETH=y
> >  CONFIG_ETH_DESIGNWARE=y
> >  CONFIG_MII=y
> > +CONFIG_SYS_NS16550=y
> >  CONFIG_SPI=y
> >  CONFIG_TIMER=y
> >  CONFIG_SPL_TIMER=y
> >  CONFIG_DESIGNWARE_APB_TIMER=y
> > -CONFIG_USE_TINY_PRINTF=y
> > +CONFIG_DESIGNWARE_SPI=y
> > +CONFIG_USB=y
> > +CONFIG_DM_USB=y
> > +CONFIG_USB_DWC2=y
> > +CONFIG_USB_STORAGE=y
> > +CONFIG_USB_GADGET=y
> > +CONFIG_USB_GADGET_DWC2_OTG=y
> > +CONFIG_USB_GADGET_DOWNLOAD=y
> > 
> 

  reply	other threads:[~2019-01-01  3:51 UTC|newest]

Thread overview: 47+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-30  8:13 [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2018-12-30  8:13 ` [U-Boot] [PATCH 1/6] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2018-12-30 15:46   ` Marek Vasut
2019-01-01  3:10     ` Chee, Tien Fong
2019-01-01 20:27       ` Marek Vasut
2019-01-03  5:07         ` Chee, Tien Fong
2019-01-03  5:27           ` Marek Vasut
2019-01-03  5:41             ` Chee, Tien Fong
2019-01-03  7:28             ` Chee, Tien Fong
2019-01-03 20:14               ` Marek Vasut
2019-01-04  0:46                 ` Chee, Tien Fong
2019-01-04  2:10                   ` Marek Vasut
2019-01-04  2:22                     ` Chee, Tien Fong
2019-01-04  2:24                       ` Marek Vasut
2019-01-04  3:10                         ` Chee, Tien Fong
2018-12-30  8:13 ` [U-Boot] [PATCH 2/6] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2018-12-30 15:45   ` Marek Vasut
2019-01-01  3:28     ` Chee, Tien Fong
2019-01-01 20:27       ` Marek Vasut
2019-01-03  4:51         ` Chee, Tien Fong
2018-12-30  8:13 ` [U-Boot] [PATCH 3/6] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2018-12-30 15:47   ` Marek Vasut
2019-01-01  3:32     ` Chee, Tien Fong
2019-01-01 20:29       ` Marek Vasut
2019-01-03  5:36         ` Chee, Tien Fong
2019-01-03 20:15           ` Marek Vasut
2019-01-04  0:40             ` Chee, Tien Fong
2019-01-15  8:16             ` Chee, Tien Fong
2019-01-15 11:34               ` Marek Vasut
2018-12-30  8:13 ` [U-Boot] [PATCH 4/6] ARM: dts: socfpga: Add missing SDMMC reset tien.fong.chee at intel.com
2018-12-30 15:48   ` Marek Vasut
2018-12-30  8:13 ` [U-Boot] [PATCH 5/6] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2018-12-30 15:51   ` Marek Vasut
2019-01-01  3:39     ` Chee, Tien Fong
2019-01-01 20:31       ` Marek Vasut
2019-01-03  5:32         ` Chee, Tien Fong
2018-12-30  8:13 ` [U-Boot] [PATCH 6/6] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2018-12-30 15:54   ` Marek Vasut
2019-01-01  3:51     ` Chee, Tien Fong [this message]
2019-01-01 20:35       ` Marek Vasut
2019-01-02  8:50         ` Chee, Tien Fong
2019-01-02 14:20           ` Marek Vasut
2018-12-30 15:44 ` [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream Marek Vasut
2019-01-01  2:52   ` Chee, Tien Fong
2019-01-01 20:36     ` Marek Vasut
2019-01-03  5:33       ` Chee, Tien Fong
2019-01-03 20:16         ` Marek Vasut

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1546314704.10462.35.camel@intel.com \
    --to=tien.fong.chee@intel.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox