From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream
Date: Thu, 3 Jan 2019 05:33:42 +0000 [thread overview]
Message-ID: <1546493622.10047.18.camel@intel.com> (raw)
In-Reply-To: <0c0e78d8-15d3-8711-7b85-e9412c06da2c@denx.de>
On Tue, 2019-01-01 at 21:36 +0100, Marek Vasut wrote:
> On 1/1/19 3:52 AM, Chee, Tien Fong wrote:
> >
> > On Sun, 2018-12-30 at 16:44 +0100, Marek Vasut wrote:
> > >
> > > On 12/30/18 9:13 AM, tien.fong.chee at intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > >
> > > > These series of patches enable peripheral bitstream being
> > > > programmed into FPGA
> > > > to get the DDR up running. This's also called early IO release,
> > > > because the
> > > > peripheral bitstream is only initializing FPGA IOs, PLL, IO48
> > > > and
> > > > DDR.
> > > >
> > > > Once DDR is up running, core bitstream from MMC which contains
> > > > user
> > > > FPGA
> > > > design would be loaded into DDR location. socfpga loadfs would
> > > > be
> > > > called to
> > > > program core bitstream into FPGA and entering user mode.
> > > >
> > > > Lastly, u-boot-dtb.img from MMC FAT partition would be loaded
> > > > to
> > > > DDR, and up
> > > > running from there.
> > > >
> > > > For this whole mechanism to work, the SDMMC flash layout would
> > > > be
> > > > designed as
> > > > shown in below:
> > > >
> > > > RAW partition:
> > > > 1. spl_w_dtb-mkpimage.bin
> > > > mkpimage -hv 1 -o spl/spl_w_dtb-mkpimage.bin spl/u-boot-spl-
> > > > dtb.bin
> > > > spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-
> > > > dtb.bin
> > > >
> > > > FAT partition contains:
> > > > Bitstreams
> > > > ----------
> > > > Early IO release method is recommended for the sake of
> > > > performance,
> > > > improve
> > > > up to 86% compare to full RBF.
> > > >
> > > > 1. ghrd_10as066n2.periph.rbf.mkimage
> > > > mkimage -A arm -T firmware -C none -O u-boot -a 0 -e 0 -n
> > > > \"RBF\"
> > > > -d
> > > > ghrd_10as066n2.periph.rbf ghrd_10as066n2.periph.rbf.mkimage
> > > >
> > > > 2. ghrd_10as066n2.core.rbf.mkimage
> > > > mkimage -A arm -T firmware -C none -O u-boot -a 0 -e 0 -n
> > > > \"RBF\"
> > > > -d
> > > > ghrd_10as066n2.core.rbf ghrd_10as066n2.core.rbf.mkimage
> > > >
> > > > OR
> > > >
> > > > 1. ghrd_10as066n2.rbf.mkimage (full RBF)
> > > > mkimage -A arm -T firmware -C none -O u-boot -a 0 -e 0 -n
> > > > \"RBF\"
> > > > -d
> > > > ghrd_10as066n2.rbf ghrd_10as066n2.rbf.mkimage
> > > >
> > > > U-Boot image
> > > > ------------
> > > > 3. u-boot-dtb.img
> > > >
> > > > For the testing purpose, these two patches are required to
> > > > apply
> > > > 1st before
> > > > applying this series of patches.
> > > > 1. [U-Boot] [PATCH] misc: fs_loader: Switching private data
> > > > allocation to DM
> > > > auto allocation
> > > > https://www.mail-archive.com/u-boot at lists.denx.de/msg308954.
> > > > html
> > > > Reviewed-by: Simon Glass <s...@chromium.org>
> > > >
> > > > 2. [U-Boot] [PATCH v2] Add support for initializing MMC
> > > > https://www.mail-archive.com/u-boot at lists.denx.de/msg310532.
> > > > html
> > > > Version 2 under review.
> > > The above should be made into documentation, since cover letters
> > > are
> > > dropped.
> > Happy new year Marek.
> Happy New Year to you too.
>
> >
> > Yeah, the document would be sent out once the implementation is
> > finalized. Hence, we need your mercy and help to get this done :-P,
> > just kidding.
> I hope you can wrap this into V7 .
Sure.
>
next prev parent reply other threads:[~2019-01-03 5:33 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-30 8:13 [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2018-12-30 8:13 ` [U-Boot] [PATCH 1/6] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2018-12-30 15:46 ` Marek Vasut
2019-01-01 3:10 ` Chee, Tien Fong
2019-01-01 20:27 ` Marek Vasut
2019-01-03 5:07 ` Chee, Tien Fong
2019-01-03 5:27 ` Marek Vasut
2019-01-03 5:41 ` Chee, Tien Fong
2019-01-03 7:28 ` Chee, Tien Fong
2019-01-03 20:14 ` Marek Vasut
2019-01-04 0:46 ` Chee, Tien Fong
2019-01-04 2:10 ` Marek Vasut
2019-01-04 2:22 ` Chee, Tien Fong
2019-01-04 2:24 ` Marek Vasut
2019-01-04 3:10 ` Chee, Tien Fong
2018-12-30 8:13 ` [U-Boot] [PATCH 2/6] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2018-12-30 15:45 ` Marek Vasut
2019-01-01 3:28 ` Chee, Tien Fong
2019-01-01 20:27 ` Marek Vasut
2019-01-03 4:51 ` Chee, Tien Fong
2018-12-30 8:13 ` [U-Boot] [PATCH 3/6] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2018-12-30 15:47 ` Marek Vasut
2019-01-01 3:32 ` Chee, Tien Fong
2019-01-01 20:29 ` Marek Vasut
2019-01-03 5:36 ` Chee, Tien Fong
2019-01-03 20:15 ` Marek Vasut
2019-01-04 0:40 ` Chee, Tien Fong
2019-01-15 8:16 ` Chee, Tien Fong
2019-01-15 11:34 ` Marek Vasut
2018-12-30 8:13 ` [U-Boot] [PATCH 4/6] ARM: dts: socfpga: Add missing SDMMC reset tien.fong.chee at intel.com
2018-12-30 15:48 ` Marek Vasut
2018-12-30 8:13 ` [U-Boot] [PATCH 5/6] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2018-12-30 15:51 ` Marek Vasut
2019-01-01 3:39 ` Chee, Tien Fong
2019-01-01 20:31 ` Marek Vasut
2019-01-03 5:32 ` Chee, Tien Fong
2018-12-30 8:13 ` [U-Boot] [PATCH 6/6] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2018-12-30 15:54 ` Marek Vasut
2019-01-01 3:51 ` Chee, Tien Fong
2019-01-01 20:35 ` Marek Vasut
2019-01-02 8:50 ` Chee, Tien Fong
2019-01-02 14:20 ` Marek Vasut
2018-12-30 15:44 ` [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream Marek Vasut
2019-01-01 2:52 ` Chee, Tien Fong
2019-01-01 20:36 ` Marek Vasut
2019-01-03 5:33 ` Chee, Tien Fong [this message]
2019-01-03 20:16 ` Marek Vasut
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