[U-Boot] [PATCH 1/6] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

Marek Vasut
2018-12-30T15:46:48Z

On 12/30/18 9:13 AM, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
>
> This patch adds description on properties about file name used for both
> peripheral bitstream and core bitstream.
>
> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> ---
> .../fpga/altera-socfpga-a10-fpga-mgr.txt | 21 ++++++++++++++++++++
> 1 files changed, 21 insertions(+), 0 deletions(-)
>
> diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> index 2fd8e7a..4552edc 100644
> --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
> @@ -7,13 +7,34 @@ Required properties:
> - The second index is for writing FPGA configuration data.
> - resets : Phandle and reset specifier for the device's reset.
> - clocks : Clocks used by the device.
> +- altr,bitstream : File name for FPGA peripheral raw binary which is used
> + to initialize FPGA IOs, PLL, IO48 and DDR.
> + or
> + File name for full RBF, consist of periph RBF and core RBF
> +- altr,bitstream-core : File name for core RBF which contains FPGA design
> + which is used to program FPGA CRAM and ERAM.
>
> Example:
>
> +- Examples for booting with early IO release, enter early user mode(periph RBF):
> +
> + fpga_mgr: fpga-mgr at ffd03000 {
> + compatible = "altr,socfpga-a10-fpga-mgr";
> + reg = <0xffd03000 0x100
> + 0xffcfe400 0x20>;
> + clocks = <&l4_mp_clk>;
> + resets = <&rst FPGAMGR_RESET>;
> + altr,bitstream = "ghrd_10as066n2.periph.rbf.mkimage";
> + altr,bitstream-core = "ghrd_10as066n2.core.rbf.mkimage";

What is this .mkimage format about ? Is that uImage ? Since it's two
files, it could probably be bundled into fitImage instead ?

> + };
> +
> +- Examples for booting with full release, enter user mode with full RBF:
> +
> fpga_mgr: fpga-mgr at ffd03000 {
> compatible = "altr,socfpga-a10-fpga-mgr";
> reg = <0xffd03000 0x100
> 0xffcfe400 0x20>;
> clocks = <&l4_mp_clk>;
> resets = <&rst FPGAMGR_RESET>;
> + altr,bitstream = "ghrd_10as066n2.rbf.mkimage";
> };
>

--
Best regards,
Marek Vasut