From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/6] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10
Date: Fri, 4 Jan 2019 03:10:52 +0000 [thread overview]
Message-ID: <1546571452.9763.2.camel@intel.com> (raw)
In-Reply-To: <0286cc5a-74fb-a687-dfdd-d7dc95b4c120@denx.de>
On Fri, 2019-01-04 at 03:24 +0100, Marek Vasut wrote:
> On 1/4/19 3:22 AM, Chee, Tien Fong wrote:
> >
> > On Fri, 2019-01-04 at 03:10 +0100, Marek Vasut wrote:
> > >
> > > On 1/4/19 1:46 AM, Chee, Tien Fong wrote:
> > > [...]
> > >
> > > >
> > > >
> > > > >
> > > > >
> > > > > >
> > > > > >
> > > > > > 2. What you means with partial loading? partial loading for
> > > > > > periph.rbf
> > > > > > or core.rbf or both rbfs?
> > > > > That you can only load the relevant image from the fitImage,
> > > > > not
> > > > > the
> > > > > entire fitImage, which lets you load the core bitstream in
> > > > > SPL.
> > > > So, you want 2 files periph.rbf.mkimage, and fitImage(contains
> > > > core.rbf) or both periph.rbf and core.rbf in one fitImage?
> > > Does it make sense ?
> > Which one you refer, 1 or 2?
> > 1. Two files => periph.rbf.mkimage, and fitImage(contains core.rbf)
> > in
> > FAT partition
> > 2. Both periph.rbf and core.rbf in one fitImage in FAT partition
> One fitImage file containing both .rbf files , stored in whatever
> storage the user needs.
Okay, let me explore feasibility of this kind implementation.
>
next prev parent reply other threads:[~2019-01-04 3:10 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-30 8:13 [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2018-12-30 8:13 ` [U-Boot] [PATCH 1/6] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2018-12-30 15:46 ` Marek Vasut
2019-01-01 3:10 ` Chee, Tien Fong
2019-01-01 20:27 ` Marek Vasut
2019-01-03 5:07 ` Chee, Tien Fong
2019-01-03 5:27 ` Marek Vasut
2019-01-03 5:41 ` Chee, Tien Fong
2019-01-03 7:28 ` Chee, Tien Fong
2019-01-03 20:14 ` Marek Vasut
2019-01-04 0:46 ` Chee, Tien Fong
2019-01-04 2:10 ` Marek Vasut
2019-01-04 2:22 ` Chee, Tien Fong
2019-01-04 2:24 ` Marek Vasut
2019-01-04 3:10 ` Chee, Tien Fong [this message]
2018-12-30 8:13 ` [U-Boot] [PATCH 2/6] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2018-12-30 15:45 ` Marek Vasut
2019-01-01 3:28 ` Chee, Tien Fong
2019-01-01 20:27 ` Marek Vasut
2019-01-03 4:51 ` Chee, Tien Fong
2018-12-30 8:13 ` [U-Boot] [PATCH 3/6] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2018-12-30 15:47 ` Marek Vasut
2019-01-01 3:32 ` Chee, Tien Fong
2019-01-01 20:29 ` Marek Vasut
2019-01-03 5:36 ` Chee, Tien Fong
2019-01-03 20:15 ` Marek Vasut
2019-01-04 0:40 ` Chee, Tien Fong
2019-01-15 8:16 ` Chee, Tien Fong
2019-01-15 11:34 ` Marek Vasut
2018-12-30 8:13 ` [U-Boot] [PATCH 4/6] ARM: dts: socfpga: Add missing SDMMC reset tien.fong.chee at intel.com
2018-12-30 15:48 ` Marek Vasut
2018-12-30 8:13 ` [U-Boot] [PATCH 5/6] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2018-12-30 15:51 ` Marek Vasut
2019-01-01 3:39 ` Chee, Tien Fong
2019-01-01 20:31 ` Marek Vasut
2019-01-03 5:32 ` Chee, Tien Fong
2018-12-30 8:13 ` [U-Boot] [PATCH 6/6] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2018-12-30 15:54 ` Marek Vasut
2019-01-01 3:51 ` Chee, Tien Fong
2019-01-01 20:35 ` Marek Vasut
2019-01-02 8:50 ` Chee, Tien Fong
2019-01-02 14:20 ` Marek Vasut
2018-12-30 15:44 ` [U-Boot] [PATCH 0/6] Add support for loading FPGA bitstream Marek Vasut
2019-01-01 2:52 ` Chee, Tien Fong
2019-01-01 20:36 ` Marek Vasut
2019-01-03 5:33 ` Chee, Tien Fong
2019-01-03 20:16 ` Marek Vasut
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