From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v7 4/7] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
Date: Fri, 1 Feb 2019 04:07:18 +0000 [thread overview]
Message-ID: <1548994038.11133.25.camel@intel.com> (raw)
In-Reply-To: <4e8ac242-8785-01fc-c798-7a29503e5df7@denx.de>
On Thu, 2019-01-31 at 15:57 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.chee at intel.com wrote:
> >
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > Update the default configuration file to enable the necessary
> > functionality
> > to get the SoCFPGA loadfs driver support. This would enable the
> > implementation of programming bitstream into FPGA from MMC.
> >
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> >
> > ---
> >
> > changes for v7
> > - Removed limit set for CONFIG_FS_FAT_MAX_CLUSTSIZE
> > ---
> > configs/socfpga_arria10_defconfig | 6 ++++++
> > 1 file changed, 6 insertions(+)
> >
> > diff --git a/configs/socfpga_arria10_defconfig
> > b/configs/socfpga_arria10_defconfig
> > index 0554f1b..fc0dfa4 100644
> > --- a/configs/socfpga_arria10_defconfig
> > +++ b/configs/socfpga_arria10_defconfig
> > @@ -27,9 +27,15 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0"
> > # CONFIG_EFI_PARTITION is not set
> > CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
> > CONFIG_ENV_IS_IN_MMC=y
> > +CONFIG_SPL_ENV_SUPPORT=y
> > CONFIG_SPL_DM=y
> > CONFIG_SPL_DM_SEQ_ALIAS=y
> > +CONFIG_SPL_DM_MMC=y
> Oddly enough, only 6/7 enables CONFIG_DW_MMC=y, so unless you apply
> also
> 6/7, this patch cannot work as intended.
Good catch!! I think all FIT related configs from 6/7 should be moved
to here because the FPGA driver now is FPGA FIT image implementation.
>
> >
> > +CONFIG_SPL_MMC_SUPPORT=y
> > +CONFIG_SPL_EXT_SUPPORT=y
> > CONFIG_SPL_FS_FAT=y
> > +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> > +CONFIG_FS_LOADER=y
> > CONFIG_FPGA_SOCFPGA=y
> > CONFIG_DM_GPIO=y
> > CONFIG_DWAPB_GPIO=y
> >
>
next prev parent reply other threads:[~2019-02-01 4:07 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 14:51 [U-Boot] [PATCH v7 0/7] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-01-31 14:54 ` Marek Vasut
2019-02-01 3:48 ` Chee, Tien Fong
2019-02-01 8:25 ` Marek Vasut
2019-02-01 16:02 ` Chee, Tien Fong
2019-02-01 20:02 ` Dalon L Westergreen
2019-02-01 20:29 ` Dalon L Westergreen
2019-02-02 2:37 ` Chee, Tien Fong
2019-02-05 8:46 ` Marek Vasut
2019-02-11 5:36 ` Chee, Tien Fong
2019-02-11 11:01 ` Marek Vasut
2019-02-11 16:33 ` Dalon L Westergreen
2019-02-11 17:01 ` Chee, Tien Fong
2019-02-11 17:19 ` Westergreen, Dalon
2019-02-12 9:35 ` Chee, Tien Fong
2019-02-12 9:43 ` Marek Vasut
2019-02-12 10:13 ` Chee, Tien Fong
2019-02-12 10:17 ` Marek Vasut
2019-02-12 13:49 ` Dalon L Westergreen
2019-02-12 14:06 ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 2/7] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:54 ` Marek Vasut
2019-02-01 3:59 ` Chee, Tien Fong
2019-02-01 8:29 ` Marek Vasut
2019-02-01 16:50 ` Chee, Tien Fong
2019-02-05 8:51 ` Marek Vasut
2019-02-11 6:23 ` Chee, Tien Fong
2019-02-11 11:06 ` Marek Vasut
2019-02-11 16:20 ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 3/7] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-01-31 14:55 ` Marek Vasut
2019-02-01 4:04 ` Chee, Tien Fong
2019-02-01 8:29 ` Marek Vasut
2019-02-01 16:50 ` Chee, Tien Fong
2019-02-13 8:22 ` Chee, Tien Fong
2019-02-13 12:00 ` Marek Vasut
2019-02-13 12:15 ` Chee, Tien Fong
2019-02-13 12:34 ` Marek Vasut
2019-02-01 20:12 ` Dalon L Westergreen
2019-02-02 3:27 ` Chee, Tien Fong
2019-02-05 8:41 ` Marek Vasut
2019-02-11 11:19 ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 4/7] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:57 ` Marek Vasut
2019-02-01 4:07 ` Chee, Tien Fong [this message]
2019-01-31 14:51 ` [U-Boot] [PATCH v7 5/7] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 6/7] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 7/7] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-01-31 14:58 ` Marek Vasut
2019-02-01 4:11 ` Chee, Tien Fong
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1548994038.11133.25.camel@intel.com \
--to=tien.fong.chee@intel.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox