From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chee, Tien Fong Date: Fri, 1 Feb 2019 04:07:18 +0000 Subject: [U-Boot] [PATCH v7 4/7] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK In-Reply-To: <4e8ac242-8785-01fc-c798-7a29503e5df7@denx.de> References: <1548946304-17460-1-git-send-email-tien.fong.chee@intel.com> <1548946304-17460-5-git-send-email-tien.fong.chee@intel.com> <4e8ac242-8785-01fc-c798-7a29503e5df7@denx.de> Message-ID: <1548994038.11133.25.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Thu, 2019-01-31 at 15:57 +0100, Marek Vasut wrote: > On 1/31/19 3:51 PM, tien.fong.chee at intel.com wrote: > > > > From: Tien Fong Chee > > > > Update the default configuration file to enable the necessary > > functionality > > to get the SoCFPGA loadfs driver support. This would enable the > > implementation of programming bitstream into FPGA from MMC. > > > > Signed-off-by: Tien Fong Chee > > > > --- > > > > changes for v7 > > - Removed limit set for CONFIG_FS_FAT_MAX_CLUSTSIZE > > --- > >  configs/socfpga_arria10_defconfig | 6 ++++++ > >  1 file changed, 6 insertions(+) > > > > diff --git a/configs/socfpga_arria10_defconfig > > b/configs/socfpga_arria10_defconfig > > index 0554f1b..fc0dfa4 100644 > > --- a/configs/socfpga_arria10_defconfig > > +++ b/configs/socfpga_arria10_defconfig > > @@ -27,9 +27,15 @@ CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" > >  # CONFIG_EFI_PARTITION is not set > >  CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" > >  CONFIG_ENV_IS_IN_MMC=y > > +CONFIG_SPL_ENV_SUPPORT=y > >  CONFIG_SPL_DM=y > >  CONFIG_SPL_DM_SEQ_ALIAS=y > > +CONFIG_SPL_DM_MMC=y > Oddly enough, only 6/7 enables CONFIG_DW_MMC=y, so unless you apply > also > 6/7, this patch cannot work as intended. Good catch!! I think all FIT related configs from 6/7 should be moved to here because the FPGA driver now is FPGA FIT image implementation. > > > > > +CONFIG_SPL_MMC_SUPPORT=y > > +CONFIG_SPL_EXT_SUPPORT=y > >  CONFIG_SPL_FS_FAT=y > > +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y > > +CONFIG_FS_LOADER=y > >  CONFIG_FPGA_SOCFPGA=y > >  CONFIG_DM_GPIO=y > >  CONFIG_DWAPB_GPIO=y > > >