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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v7 7/7] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
Date: Fri, 1 Feb 2019 04:11:44 +0000	[thread overview]
Message-ID: <1548994303.11133.29.camel@intel.com> (raw)
In-Reply-To: <3fa6f0f9-9c37-ba3c-47a2-acca5294429d@denx.de>

On Thu, 2019-01-31 at 15:58 +0100, Marek Vasut wrote:
> On 1/31/19 3:51 PM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > After some series of patches to maximise reusable of memory pool,
> > here come
> > to result of reasonable size required for whole SDMMC boot working
> > on A10
> > SoCDK. Size required come from default max cluster(0x100000) +
> The max cluster size is 0x10000 , one zero too many in the
> description.
Good catch!! Blurry vision on my eyes when i was working too late :).
> 
> > 
> > others(0x2000) + additional memory for headroom(0x3000).
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > ---
> > 
> > changes for v7
> > - Added 0x3000 for memory headroom.
> > ---
> >  include/configs/socfpga_common.h | 4 ++--
> >  1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 4551cb2..548b458 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -1,6 +1,6 @@
> >  /* SPDX-License-Identifier: GPL-2.0+ */
> >  /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
> >   */
> >  #ifndef __CONFIG_SOCFPGA_COMMON_H__
> >  #define __CONFIG_SOCFPGA_COMMON_H__
> > @@ -258,7 +258,7 @@ unsigned int
> > cm_get_qspi_controller_clk_hz(void);
> >  #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> >  /* SPL memory allocation configuration, this is for FAT
> > implementation */
> >  #ifndef CONFIG_SYS_SPL_MALLOC_START
> > -#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
> > +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00015000
> >  #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SI
> > ZE - \
> >  					 CONFIG_SYS_SPL_MALLOC_SIZ
> > E + \
> >  					 CONFIG_SYS_INIT_RAM_ADDR)
> > 
> 

      reply	other threads:[~2019-02-01  4:11 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-31 14:51 [U-Boot] [PATCH v7 0/7] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-01-31 14:54   ` Marek Vasut
2019-02-01  3:48     ` Chee, Tien Fong
2019-02-01  8:25       ` Marek Vasut
2019-02-01 16:02         ` Chee, Tien Fong
2019-02-01 20:02           ` Dalon L Westergreen
2019-02-01 20:29             ` Dalon L Westergreen
2019-02-02  2:37               ` Chee, Tien Fong
2019-02-05  8:46           ` Marek Vasut
2019-02-11  5:36             ` Chee, Tien Fong
2019-02-11 11:01               ` Marek Vasut
2019-02-11 16:33                 ` Dalon L Westergreen
2019-02-11 17:01                 ` Chee, Tien Fong
2019-02-11 17:19                   ` Westergreen, Dalon
2019-02-12  9:35                     ` Chee, Tien Fong
2019-02-12  9:43                       ` Marek Vasut
2019-02-12 10:13                         ` Chee, Tien Fong
2019-02-12 10:17                           ` Marek Vasut
2019-02-12 13:49                             ` Dalon L Westergreen
2019-02-12 14:06                               ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 2/7] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:54   ` Marek Vasut
2019-02-01  3:59     ` Chee, Tien Fong
2019-02-01  8:29       ` Marek Vasut
2019-02-01 16:50         ` Chee, Tien Fong
2019-02-05  8:51           ` Marek Vasut
2019-02-11  6:23             ` Chee, Tien Fong
2019-02-11 11:06               ` Marek Vasut
2019-02-11 16:20                 ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 3/7] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-01-31 14:55   ` Marek Vasut
2019-02-01  4:04     ` Chee, Tien Fong
2019-02-01  8:29       ` Marek Vasut
2019-02-01 16:50         ` Chee, Tien Fong
2019-02-13  8:22         ` Chee, Tien Fong
2019-02-13 12:00           ` Marek Vasut
2019-02-13 12:15             ` Chee, Tien Fong
2019-02-13 12:34               ` Marek Vasut
2019-02-01 20:12   ` Dalon L Westergreen
2019-02-02  3:27     ` Chee, Tien Fong
2019-02-05  8:41       ` Marek Vasut
2019-02-11 11:19         ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 4/7] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:57   ` Marek Vasut
2019-02-01  4:07     ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 5/7] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 6/7] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 7/7] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-01-31 14:58   ` Marek Vasut
2019-02-01  4:11     ` Chee, Tien Fong [this message]

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