[U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

tien.fong.chee at intel.com
2019-01-31T14:51:38Z

From: Tien Fong Chee <tien.fong.chee@intel.com>

This patch adds description on properties about file name used for both
peripheral bitstream and core bitstream.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>

---

changes for v7
- Provided example of setting FPGA FIT image for both early IO release
and full release FPGA configuration.
---
.../fpga/altera-socfpga-a10-fpga-mgr.txt | 34 +++++++++++++++++++++-
1 file changed, 33 insertions(+), 1 deletion(-)

diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
index 2fd8e7a..5f81a32 100644
--- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
+++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt
@@ -7,8 +7,39 @@ Required properties:
- The second index is for writing FPGA configuration data.
- resets : Phandle and reset specifier for the device's reset.
- clocks : Clocks used by the device.
+- altr,bitstream : File name for FPGA peripheral bitstream which is used
+ to initialize FPGA IOs, PLL, IO48 and DDR. This bitstream is
+ required to get DDR up running.
+ or
+ File name for full bitstream, consist of peripheral bitstream
+ and core bitstream.
+- altr,bitstream-core(optional) : File name for core bitstream which contains
+ FPGA design which is used to program FPGA CRAM
+ and ERAM.

-Example:
+Example: Bundles both peripheral bitstream and core bitstream into FIT image
+ called fit_spl_fpga.itb. This FIT image can be created through running
+ this command: tools/mkimage
+ -E -p 400
+ -f board/altera/arria10-socdk/fit_spl_fpga.its
+ fit_spl_fpga.itb
+
+ For details of describing structure and contents of the FIT image,
+ please refer board/altera/arria10-socdk/fit_spl_fpga.its
+
+- Examples for booting with early IO release, and enter early user mode:
+
+ fpga_mgr: fpga-mgr at ffd03000 {
+ compatible = "altr,socfpga-a10-fpga-mgr";
+ reg = <0xffd03000 0x100
+ 0xffcfe400 0x20>;
+ clocks = <&l4_mp_clk>;
+ resets = <&rst FPGAMGR_RESET>;
+ altr,bitstream = "fit_spl_fpga.itb";
+ altr,bitstream-core = "fit_spl_fpga.itb";
+ };
+
+- Examples for booting with full release, enter user mode with full bitstream:

fpga_mgr: fpga-mgr at ffd03000 {
compatible = "altr,socfpga-a10-fpga-mgr";
@@ -16,4 +47,5 @@ Example:
0xffcfe400 0x20>;
clocks = <&l4_mp_clk>;
resets = <&rst FPGAMGR_RESET>;
+ altr,bitstream = "fit_spl_fpga.itb";
};
--
2.2.0