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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10
Date: Tue, 12 Feb 2019 10:13:54 +0000	[thread overview]
Message-ID: <1549966432.10168.9.camel@intel.com> (raw)
In-Reply-To: <c05becf0-1bbd-a1ce-ab5d-3129dad20c1d@denx.de>

On Tue, 2019-02-12 at 10:43 +0100, Marek Vasut wrote:
> On 2/12/19 10:35 AM, Chee, Tien Fong wrote:
> [...]
> 
> > 
> > > 
> > > my preference for the fit image would be
> > > 
> > > ...
> > > images {
> > >   fpga at 1 {
> > > 	description = "FPGA Periph";
> > > 	...
> > > 	type = "fpga_periph";
> > > 	...
> > >   }
> > >   fpga at 2 {
> > > 	description = "FPGA Core";
> > > 	...
> > > 	type = "fpga" or
> > > "fpga_core";
> > I'm good with "fpga".
> > > 
> > > 	...
> > >   }
> > > };
> > > configurations {
> > >   default = "config at 1"
> > >   config at 1 {
> > >       fpga = "fpga at 1";  // periph only
> > >   };
> > >   config at 2 {
> > >       fpga = "fpga at 1", "fpga at 2";
> > >   };
> > > };
> > > 
> > > with the expectation that the order of fpga at 1 and fpga at 2 in confi
> > > g at 2
> > > is not relevant.  the code should find the fpga_periph type and
> > > program
> > > it first.  just my comment, i dont like rellying on the order or
> > > name.
> > I can add support for above implementation although this adds more
> > complexity to the driver.
> You can have fpga node and e.g. fpga-name node in the configurations
> section to discern which phandle there is the core and which is the
> peripheral RBF. Would that work ?
> 
So something like that?

...

images {
  fpga-periph at 1 {
	description = "FPGA Periph";
	...
	type = "fpga_periph";
	...
  }
  fpga-core at 2 {
	description = "FPGA Core";
	...
	type = "fpga";
	...
  }
};
configurations {
  default = "config at 1"
  config at 1 {
      fpga = "fpga-periph at 1";  // periph only
  };
  config at 2 {
      fpga = "fpga-periph at 1", "fpga-core at 2";
  };
};

> > 
> > Marek, are you OK with this implementation?
> Looks OK to me. Dalon ?
> 
> [...]

  reply	other threads:[~2019-02-12 10:13 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-31 14:51 [U-Boot] [PATCH v7 0/7] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-01-31 14:54   ` Marek Vasut
2019-02-01  3:48     ` Chee, Tien Fong
2019-02-01  8:25       ` Marek Vasut
2019-02-01 16:02         ` Chee, Tien Fong
2019-02-01 20:02           ` Dalon L Westergreen
2019-02-01 20:29             ` Dalon L Westergreen
2019-02-02  2:37               ` Chee, Tien Fong
2019-02-05  8:46           ` Marek Vasut
2019-02-11  5:36             ` Chee, Tien Fong
2019-02-11 11:01               ` Marek Vasut
2019-02-11 16:33                 ` Dalon L Westergreen
2019-02-11 17:01                 ` Chee, Tien Fong
2019-02-11 17:19                   ` Westergreen, Dalon
2019-02-12  9:35                     ` Chee, Tien Fong
2019-02-12  9:43                       ` Marek Vasut
2019-02-12 10:13                         ` Chee, Tien Fong [this message]
2019-02-12 10:17                           ` Marek Vasut
2019-02-12 13:49                             ` Dalon L Westergreen
2019-02-12 14:06                               ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 2/7] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:54   ` Marek Vasut
2019-02-01  3:59     ` Chee, Tien Fong
2019-02-01  8:29       ` Marek Vasut
2019-02-01 16:50         ` Chee, Tien Fong
2019-02-05  8:51           ` Marek Vasut
2019-02-11  6:23             ` Chee, Tien Fong
2019-02-11 11:06               ` Marek Vasut
2019-02-11 16:20                 ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 3/7] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-01-31 14:55   ` Marek Vasut
2019-02-01  4:04     ` Chee, Tien Fong
2019-02-01  8:29       ` Marek Vasut
2019-02-01 16:50         ` Chee, Tien Fong
2019-02-13  8:22         ` Chee, Tien Fong
2019-02-13 12:00           ` Marek Vasut
2019-02-13 12:15             ` Chee, Tien Fong
2019-02-13 12:34               ` Marek Vasut
2019-02-01 20:12   ` Dalon L Westergreen
2019-02-02  3:27     ` Chee, Tien Fong
2019-02-05  8:41       ` Marek Vasut
2019-02-11 11:19         ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 4/7] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:57   ` Marek Vasut
2019-02-01  4:07     ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 5/7] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 6/7] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 7/7] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-01-31 14:58   ` Marek Vasut
2019-02-01  4:11     ` Chee, Tien Fong

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