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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v7 3/7] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
Date: Wed, 13 Feb 2019 08:22:01 +0000	[thread overview]
Message-ID: <1550046120.10013.3.camel@intel.com> (raw)
In-Reply-To: <76aa99ad-8f89-1ddc-9686-733a5362509d@denx.de>

On Fri, 2019-02-01 at 09:29 +0100, Marek Vasut wrote:
> On 2/1/19 5:04 AM, Chee, Tien Fong wrote:
> > 
> > On Thu, 2019-01-31 at 15:55 +0100, Marek Vasut wrote:
> > > 
> > > On 1/31/19 3:51 PM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > Add FPGA driver to support program FPGA with FPGA bitstream
> > > > loading
> > > > from
> > > > filesystem. The driver are designed based on generic firmware
> > > > loader
> > > > framework. The driver can handle FPGA program operation from
> > > > loading FPGA
> > > > bitstream in flash to memory and then to program FPGA.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > ---
> > > > 
> > > > changes for v7
> > > > - Restructure the FPGA driver to support both peripheral
> > > > bitstream
> > > > and core
> > > >   bitstream bundled into FIT image.
> > > > - Support loadable property for core bitstream. User can set
> > > > loadable
> > > >   in DDR for better performance. This loading would be done in
> > > > one
> > > > large
> > > >   chunk instead of chunk by chunk loading with small memory
> > > > buffer.
> > > > ---
> > > >  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts       |  18 +
> > > >  .../include/mach/fpga_manager_arria10.h            |  39 +-
> > > >  drivers/fpga/socfpga_arria10.c                     | 417
> > > > ++++++++++++++++++++-
> > > >  3 files changed, 457 insertions(+), 17 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > index 998d811..dc55618 100644
> > > > --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> > > > @@ -18,6 +18,24 @@
> > > >  /dts-v1/;
> > > >  #include "socfpga_arria10_socdk.dtsi"
> > > >  
> > > > +/ {
> > > > +	chosen {
> > > > +		firmware-loader = &fs_loader0;
> > > Shouldn't this be <&fs_loader0>; ?
> > > How did this even pass the DTC ?
> > So <> is compulsory required for phandle? No error complaint from
> > DTC.
> Yes
I just checked the codes, this &fs_loader0 without <> is valid, because
this is not a phandle, instead it is a label which will be expanded to
the node's full path.
> 

  parent reply	other threads:[~2019-02-13  8:22 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-31 14:51 [U-Boot] [PATCH v7 0/7] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-01-31 14:54   ` Marek Vasut
2019-02-01  3:48     ` Chee, Tien Fong
2019-02-01  8:25       ` Marek Vasut
2019-02-01 16:02         ` Chee, Tien Fong
2019-02-01 20:02           ` Dalon L Westergreen
2019-02-01 20:29             ` Dalon L Westergreen
2019-02-02  2:37               ` Chee, Tien Fong
2019-02-05  8:46           ` Marek Vasut
2019-02-11  5:36             ` Chee, Tien Fong
2019-02-11 11:01               ` Marek Vasut
2019-02-11 16:33                 ` Dalon L Westergreen
2019-02-11 17:01                 ` Chee, Tien Fong
2019-02-11 17:19                   ` Westergreen, Dalon
2019-02-12  9:35                     ` Chee, Tien Fong
2019-02-12  9:43                       ` Marek Vasut
2019-02-12 10:13                         ` Chee, Tien Fong
2019-02-12 10:17                           ` Marek Vasut
2019-02-12 13:49                             ` Dalon L Westergreen
2019-02-12 14:06                               ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 2/7] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:54   ` Marek Vasut
2019-02-01  3:59     ` Chee, Tien Fong
2019-02-01  8:29       ` Marek Vasut
2019-02-01 16:50         ` Chee, Tien Fong
2019-02-05  8:51           ` Marek Vasut
2019-02-11  6:23             ` Chee, Tien Fong
2019-02-11 11:06               ` Marek Vasut
2019-02-11 16:20                 ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 3/7] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-01-31 14:55   ` Marek Vasut
2019-02-01  4:04     ` Chee, Tien Fong
2019-02-01  8:29       ` Marek Vasut
2019-02-01 16:50         ` Chee, Tien Fong
2019-02-13  8:22         ` Chee, Tien Fong [this message]
2019-02-13 12:00           ` Marek Vasut
2019-02-13 12:15             ` Chee, Tien Fong
2019-02-13 12:34               ` Marek Vasut
2019-02-01 20:12   ` Dalon L Westergreen
2019-02-02  3:27     ` Chee, Tien Fong
2019-02-05  8:41       ` Marek Vasut
2019-02-11 11:19         ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 4/7] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:57   ` Marek Vasut
2019-02-01  4:07     ` Chee, Tien Fong
2019-01-31 14:51 ` [U-Boot] [PATCH v7 5/7] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 6/7] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-01-31 14:51 ` [U-Boot] [PATCH v7 7/7] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-01-31 14:58   ` Marek Vasut
2019-02-01  4:11     ` Chee, Tien Fong

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