[U-Boot] [PATCH v8 1/8] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Thu, 2019-02-14 at 11:34 +0100, Marek Vasut wrote:
> On 2/14/19 6:55 AM, Chee, Tien Fong wrote:
> > 
> > On Wed, 2019-02-13 at 17:07 +0100, Marek Vasut wrote:
> > > 
> > > On 2/13/19 3:18 PM, tien.fong.chee at intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > This patch adds description on properties about file name used
> > > > for
> > > > both
> > > > peripheral bitstream and core bitstream.
> > > > 
> > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > 
> > > > ---
> > > > 
> > > > changes for v8
> > > > - Removed explanation about support for altr,bitstream-core
> > > > 
> > > > changes for v7
> > > > - Provided example of setting FPGA FIT image for both early IO
> > > > release
> > > >   and full release FPGA configuration.
> > > > ---
> > > >  .../fpga/altera-socfpga-a10-fpga-mgr.txt           | 26
> > > > +++++++++++++++++++++-
> > > >  1 file changed, 25 insertions(+), 1 deletion(-)
> > > > 
> > > > diff --git a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > fpga-
> > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > fpga-
> > > > mgr.txt
> > > > index 2fd8e7a..da210bf 100644
> > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > mgr.txt
> > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-
> > > > mgr.txt
> > > > @@ -7,8 +7,31 @@ Required properties:
> > > >                 - The second index is for writing FPGA
> > > > configuration data.
> > > >  - resets     : Phandle and reset specifier for the device's
> > > > reset.
> > > >  - clocks     : Clocks used by the device.
> > > > +- altr,bitstream : Fit image file name for both FPGA
> > > > peripheral
> > > > bitstream,
> > > > +		   FPGA core bitstream and full bitstream.
> > > So the file contains three bitstreams ? I thought we can load
> > > only
> > > the
> > > core here.
> > Here is for telling FPGA driver which fitImage file gonna be
> > processed.
> > You can put whatever bitstreams in fitImage. Then, in the default
> > configuration, you can tell SPL FPGA driver program which
> > bitstream, it
> > could be both periph.rbf and core.rbf or just programming
> > periph.rbf
> > only.
> Ah, OK
> 
> > 
> > > 
> > > > 
> > > > -Example:
> > > > +		   Full bitstream, consist of peripheral
> > > > bitstream
> > > > and core
> > > > +		   bitstream.
> > > > +
> > > > +		   FPGA peripheral bitstream is used to
> > > > initialize
> > > > FPGA IOs,
> > > > +		   PLL, IO48 and DDR. This bitstream is
> > > > required
> > > > to get DDR up
> > > > +		   running.
> > > > +
> > > > +		   FPGA core bitstream contains FPGA design
> > > > which
> > > > is used to
> > > > +		   program FPGA CRAM and ERAM.
> > > > +
> > > > +Example: Bundles both peripheral bitstream and core bitstream
> > > > into
> > > > FIT image
> > > > +	 called fit_spl_fpga.itb. This FIT image can be
> > > > created
> > > > through running
> > > > +	 this command: tools/mkimage
> > > > +		       -E -p 400
> > > Is the padding still required ?
> > Yes, i think that padding method should be sufficient for all use
> > cases, i guess both NAND and QSPI may need this also.
> > 
> > You want me to support data offset(without padding) also?
> I think you should drop the padding, it seems to be workaround ?
I can add the data offset support, user is free to use either one of
them.
>