From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chee, Tien Fong <tien.fong.chee@intel.com>
Date: Tue, 26 Feb 2019 14:31:21 +0000
Subject: [U-Boot] [PATCH v9 2/7] ARM: socfpga: Add default FPGA
 bitstream fitImage for Arria10 SoCDK
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 <1550548041-32682-3-git-send-email-tien.fong.chee@intel.com>
 <5d3593b5-e55c-bbd7-8d32-ba15040a88db@monstr.eu>
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On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote:
> On 19. 02. 19 4:47, tien.fong.chee at intel.com wrote:
> >=20
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> >=20
> > Add default fitImage file bundling FPGA bitstreams for Arria10.
> >=20
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> >=20
> > ---
> >=20
> > changes for v8
> > - Reordered the images and fpga configurations.
> > - Removed the load property at core image.
> >=20
> > changes for v8
> No reason to have separate v8 changes.
Sorry for typo, that's v9.
>=20
> >=20
> > - Changed the FPGA node name to fpga-core and fpga-periph for both
> > core and
> > =C2=A0 periph bitstreams respectively.
> M
>=20