From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ley Foon Tan Date: Wed, 27 Feb 2019 13:28:27 +0800 Subject: [U-Boot] [PATCH] spi: cadence_qspi: Add quad write support In-Reply-To: References: <1551169746-36031-1-git-send-email-ley.foon.tan@intel.com> Message-ID: <1551245307.39221.0.camel@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit To: u-boot@lists.denx.de On Wed, 2019-02-27 at 10:38 +0530, Vignesh R wrote: > > On 26/02/19 1:59 PM, Ley Foon Tan wrote: > > > > Use quad write if SPI_TX_QUAD flag is set. > > > How was the patch tested? Could you add that info to commit msg? Tested on Stratix 10 SoC board. Will update commit message. > > > > > Signed-off-by: Ley Foon Tan > > --- > >  drivers/spi/cadence_qspi.c     | 2 +- > >  drivers/spi/cadence_qspi.h     | 2 +- > >  drivers/spi/cadence_qspi_apb.c | 7 ++++++- > >  3 files changed, 8 insertions(+), 3 deletions(-) > >  mode change 100644 => 100755 drivers/spi/cadence_qspi.c > >  mode change 100644 => 100755 drivers/spi/cadence_qspi.h > >  mode change 100644 => 100755 drivers/spi/cadence_qspi_apb.c > > > Why are the permissions being changed? Please keep it as is Change it accidentally. Will fix this. > > > > > diff --git a/drivers/spi/cadence_qspi.c > > b/drivers/spi/cadence_qspi.c > > old mode 100644 > > new mode 100755 > > index 11fce9c4fe..efdb178450 > > --- a/drivers/spi/cadence_qspi.c > > +++ b/drivers/spi/cadence_qspi.c > > @@ -256,7 +256,7 @@ static int cadence_spi_xfer(struct udevice > > *dev, unsigned int bitlen, > >   break; > >   case CQSPI_INDIRECT_WRITE: > >   err = > > cadence_qspi_apb_indirect_write_setup > > - (plat, priv->cmd_len, cmd_buf); > > + (plat, priv->cmd_len, dm_plat- > > >mode, cmd_buf); > >   if (!err) { > >   err = > > cadence_qspi_apb_indirect_write_execute > >   (plat, data_bytes, dout); > > diff --git a/drivers/spi/cadence_qspi.h > > b/drivers/spi/cadence_qspi.h > > old mode 100644 > > new mode 100755 > > index 055900def0..b491407130 > > --- a/drivers/spi/cadence_qspi.h > > +++ b/drivers/spi/cadence_qspi.h > > @@ -60,7 +60,7 @@ int cadence_qspi_apb_indirect_read_setup(struct > > cadence_spi_platdata *plat, > >  int cadence_qspi_apb_indirect_read_execute(struct > > cadence_spi_platdata *plat, > >   unsigned int rxlen, u8 *rxbuf); > >  int cadence_qspi_apb_indirect_write_setup(struct > > cadence_spi_platdata *plat, > > - unsigned int cmdlen, const u8 *cmdbuf); > > + unsigned int cmdlen, unsigned int tx_width, const u8 > > *cmdbuf); > >  int cadence_qspi_apb_indirect_write_execute(struct > > cadence_spi_platdata *plat, > >   unsigned int txlen, const u8 *txbuf); > >   > > diff --git a/drivers/spi/cadence_qspi_apb.c > > b/drivers/spi/cadence_qspi_apb.c > > old mode 100644 > > new mode 100755 > > index a8af352030..55a7501913 > > --- a/drivers/spi/cadence_qspi_apb.c > > +++ b/drivers/spi/cadence_qspi_apb.c > > @@ -77,6 +77,7 @@ > >   > >  #define CQSPI_REG_WR_INSTR 0x08 > >  #define CQSPI_REG_WR_INSTR_OPCODE_LSB 0 > > +#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16 > >   > >  #define CQSPI_REG_DELAY 0x0C > >  #define CQSPI_REG_DELAY_TSLCH_LSB 0 > > @@ -686,7 +687,7 @@ failrd: > >   > >  /* Opcode + Address (3/4 bytes) */ > >  int cadence_qspi_apb_indirect_write_setup(struct > > cadence_spi_platdata *plat, > > - unsigned int cmdlen, const u8 *cmdbuf) > > + unsigned int cmdlen, unsigned int tx_width, const u8 > > *cmdbuf) > >  { > >   unsigned int reg; > >   unsigned int addr_bytes = cmdlen > 4 ? 4 : 3; > > @@ -702,6 +703,10 @@ int > > cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata > > *plat, > >   > >   /* Configure the opcode */ > >   reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB; > > + > > + if (tx_width & SPI_TX_QUAD) > > + reg |= CQSPI_INST_TYPE_QUAD << > > CQSPI_REG_WR_INSTR_TYPE_DATA_LSB; > > + > >   writel(reg, plat->regbase + CQSPI_REG_WR_INSTR); > >   > >   /* Setup write address. */ > >