[U-Boot] [PATCH v9 1/7] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Wed, 2019-02-27 at 10:13 +0100, Michal Simek wrote:
> On 27. 02. 19 7:37, Chee, Tien Fong wrote:
> > 
> > On Tue, 2019-02-26 at 07:58 -0800, Dalon L Westergreen wrote:
> > > 
> > > On Tue, 2019-02-26 at 16:42 +0100, Michal Simek wrote:
> > > > 
> > > > 
> > > > On 26. 02. 19 15:28, Chee, Tien Fong wrote:
> > > > > 
> > > > > 
> > > > > On Tue, 2019-02-26 at 15:06 +0100, Michal Simek wrote:
> > > > > > 
> > > > > > 
> > > > > > On 19. 02. 19 4:47, tien.fong.chee at intel.com wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > > 
> > > > > > > This patch adds description on properties about file name
> > > > > > > used for
> > > > > > > both
> > > > > > > peripheral bitstream and core bitstream.
> > > > > > > 
> > > > > > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > > > > > > 
> > > > > > > ---
> > > > > > > 
> > > > > > > changes for v8
> > > > > > > - Removed explanation about support for altr,bitstream-
> > > > > > > core
> > > > > > > 
> > > > > > > changes for v7
> > > > > > > - Provided example of setting FPGA FIT image for both
> > > > > > > early
> > > > > > > IO
> > > > > > > release
> > > > > > >   and full release FPGA configuration.
> > > > > > > ---
> > > > > > >  .../fpga/altera-socfpga-a10-fpga-mgr.txt           | 26
> > > > > > > +++++++++++++++++++++-
> > > > > > >  1 file changed, 25 insertions(+), 1 deletion(-)
> > > > > > > 
> > > > > > > diff --git a/doc/device-tree-bindings/fpga/altera-
> > > > > > > socfpga-
> > > > > > > a10-fpga-
> > > > > > > mgr.txt b/doc/device-tree-bindings/fpga/altera-socfpga-
> > > > > > > a10-
> > > > > > > fpga-
> > > > > > > mgr.txt
> > > > > > > index 2fd8e7a..da210bf 100644
> > > > > > > --- a/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > > fpga-
> > > > > > > mgr.txt
> > > > > > > +++ b/doc/device-tree-bindings/fpga/altera-socfpga-a10-
> > > > > > > fpga-
> > > > > > > mgr.txt
> > > > > > > @@ -7,8 +7,31 @@ Required properties:
> > > > > > >                 - The second index is for writing FPGA
> > > > > > > configuration data.
> > > > > > >  - resets     : Phandle and reset specifier for the
> > > > > > > device's
> > > > > > > reset.
> > > > > > >  - clocks     : Clocks used by the device.
> > > > > > > +- altr,bitstream : Fit image file name for both FPGA
> > > > > > > peripheral
> > > > > > > bitstream,
> > > > > > > +		   FPGA core bitstream and full
> > > > > > > bitstream.
> > > > > > >  
> > > > > > By adding new required property you are automatically
> > > > > > saying
> > > > > > that you
> > > > > > want to break all current users.
> > > > > This is company's product specific property, that's why with
> > > > > prefix
> > > > > "altr". DT allows that ,right?
> > > > no issue with altr prefix. Issue is that you add a required
> > > > property and
> > > > breaking all current users.
> > > > It should be optional.
> > > This parameter is only for Arria10, which at this point is not
> > > fully
> > > supported
> > > in mainline uboot.  So this doesnt affect any existing designs,
> > > no?
> > Yeah, how this breaking all current users? This property in only
> > used
> > for the A10 fpga driver with fit implementation.
> That you use latest u-boot with previous DT(or our of tree DT which
> doesn't have this property).
Sorry, i'm still not getting you. My understanding "breaking" means the
existing driver would stop working after A10 DT is applied.
May be you can tell us breaking what driver?

What you means with previous DT? Which DT you means? This series of
patches are the 1st one fully support A10 SDMMC in mainline.

How this related to your DT?

Thanks,
TF