From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chee, Tien Fong <tien.fong.chee@intel.com>
Date: Tue, 5 Mar 2019 15:56:54 +0000
Subject: [U-Boot] [PATCH v10 0/9] Add support for loading FPGA bitstream
In-Reply-To: <41fb76f6-6de7-235f-9fed-97f3e3b4d417@denx.de>
References: <20190305155349.24367-1-tien.fong.chee@intel.com>
 <41fb76f6-6de7-235f-9fed-97f3e3b4d417@denx.de>
Message-ID: <1551801413.12474.2.camel@intel.com>
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To: u-boot@lists.denx.de

On Tue, 2019-03-05 at 16:54 +0100, Marek Vasut wrote:
> On 3/5/19 4:53 PM, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > This version mainly resolved some comments from Simek in [v9].
> > 
> > This series is working on top of u-boot.git http://git.denx.de/u-bo
> > ot.git
> > 
> > These patches are required before applying this series of patches
> > 1. [U-Boot,v4] misc: fs_loader: Add support for initializing block
> > device
> > https://patchwork.ozlabs.org/project/uboot/list/?series=89282(done
> > review)
> > 
> > 3. [U-Boot] misc: fs_loader: Replace label with DT phandle
> > https://patchwork.ozlabs.org/project/uboot/list/?series=92167(under
> >  review)
> > 
> > [v9]: https://www.mail-archive.com/u-boot at lists.denx.de/msg316086.h
> > tml
> > [v8]: https://www.mail-archive.com/u-boot at lists.denx.de/msg316086.h
> > tml
> > [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.h
> > tml
> > 
> > Tien Fong Chee (9):
> >   ARM: socfpga: Description on FPGA bitstream type and file name
> > for
> >     Arria 10
> >   ARM: socfpga: Add default FPGA bitstream fitImage for Arria10
> > SoCDK
> >   ARM: socfpga: Cleaning up the messages
> >   ARM: socfpga: Move the watchdog reset to the looping location
> >   ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream
> > loading
> >   ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
> >   spl : socfpga: Implement fpga bitstream loading with socfpga
> > loadfs
> >   ARM: socfpga: Synchronize the configuration for A10 SoCDK
> >   ARM: socfpga: Increase Malloc pool size to support FAT filesystem
> > in
> >     SPL
> > 
> >  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts       |  17 +
> >  .../include/mach/fpga_manager_arria10.h            |  40 +-
> >  arch/arm/mach-socfpga/spl_a10.c                    |  31 +-
> >  board/altera/arria10-socdk/fit_spl_fpga.its        |  38 ++
> >  configs/socfpga_arria10_defconfig                  |  21 +-
> >  .../fpga/altera-socfpga-a10-fpga-mgr.txt           |  26 +-
> >  drivers/fpga/socfpga_arria10.c                     | 514
> > ++++++++++++++++++++-
> >  include/configs/socfpga_common.h                   |   4 +-
> >  include/image.h                                    |   4 +
> >  9 files changed, 663 insertions(+), 32 deletions(-)
> >  create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
> > 
> Is this actually V11 ?
Okay.
>