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From: Chee, Tien Fong <tien.fong.chee@intel.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v11 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL
Date: Wed, 6 Mar 2019 02:04:26 +0000	[thread overview]
Message-ID: <1551837866.9776.1.camel@intel.com> (raw)
In-Reply-To: <f7f11495-607b-7600-0179-17a9e6c4c41f@gmail.com>

On Tue, 2019-03-05 at 21:05 +0100, Simon Goldschmidt wrote:
> Am 05.03.2019 um 17:23 schrieb tien.fong.chee at intel.com:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > After some series of patches to maximise reusable of memory pool,
> > here come
> > to result of reasonable size required for whole SDMMC boot working
> > on A10
> > SoCDK. Size required come from default max cluster(0x10000) +
> > others(0x2000) + additional memory for headroom(0x3000).
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > ---
> > 
> > changes for v7
> > - Added 0x3000 for memory headroom.
> > ---
> >   include/configs/socfpga_common.h | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 4551cb29bc..548b458e78 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -1,6 +1,6 @@
> >   /* SPDX-License-Identifier: GPL-2.0+ */
> >   /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
> >    */
> >   #ifndef __CONFIG_SOCFPGA_COMMON_H__
> >   #define __CONFIG_SOCFPGA_COMMON_H__
> > @@ -258,7 +258,7 @@ unsigned int
> > cm_get_qspi_controller_clk_hz(void);
> >   #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> >   /* SPL memory allocation configuration, this is for FAT
> > implementation */
> >   #ifndef CONFIG_SYS_SPL_MALLOC_START
> > -#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
> > +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00015000
> This will clash with my series here:
> https://patchwork.ozlabs.org/patch/1051451/
> 
> Any chance you could test that on A10? I only have a cyclone 5.
Okay, let me trying to test your series.
> 
Thanks,
TF
> 
> 
> > 
> >   #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_S
> > IZE - \
> >   					 CONFIG_SYS_SPL_MALLOC_SI
> > ZE + \
> >   					 CONFIG_SYS_INIT_RAM_ADDR
> > )
> > 

  reply	other threads:[~2019-03-06  2:04 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-05 16:23 [U-Boot] [PATCH v11 0/9] Add support for loading FPGA bitstream tien.fong.chee at intel.com
2019-03-05 16:23 ` [U-Boot] [PATCH v11 1/9] ARM: socfpga: Description on FPGA bitstream type and file name for Arria 10 tien.fong.chee at intel.com
2019-03-05 19:12   ` Dinh Nguyen
2019-03-07  7:51     ` Chee, Tien Fong
2019-03-07  8:18       ` Marek Vasut
2019-03-07  8:30         ` Chee, Tien Fong
2019-03-07  8:38           ` Marek Vasut
2019-03-07  8:56             ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 2/9] ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK tien.fong.chee at intel.com
2019-03-05 16:23 ` [U-Boot] [PATCH v11 3/9] ARM: socfpga: Cleaning up the messages tien.fong.chee at intel.com
2019-03-06  4:31   ` Dinh Nguyen
2019-03-07  7:57     ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 4/9] ARM: socfpga: Move the watchdog reset to the looping location tien.fong.chee at intel.com
2019-03-06  4:35   ` Dinh Nguyen
2019-03-07  8:04     ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 5/9] ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading tien.fong.chee at intel.com
2019-03-05 16:23 ` [U-Boot] [PATCH v11 6/9] ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK tien.fong.chee at intel.com
2019-03-06  4:11   ` Dinh Nguyen
2019-03-07  8:06     ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 7/9] spl : socfpga: Implement fpga bitstream loading with socfpga loadfs tien.fong.chee at intel.com
2019-03-05 16:23 ` [U-Boot] [PATCH v11 8/9] ARM: socfpga: Synchronize the configuration for A10 SoCDK tien.fong.chee at intel.com
2019-03-06  4:54   ` Dinh Nguyen
2019-03-07  8:14     ` Chee, Tien Fong
2019-03-05 16:23 ` [U-Boot] [PATCH v11 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL tien.fong.chee at intel.com
2019-03-05 20:05   ` Simon Goldschmidt
2019-03-06  2:04     ` Chee, Tien Fong [this message]
2019-03-07  7:07     ` Chee, Tien Fong
2019-03-07  8:10       ` Simon Goldschmidt
2019-03-07  8:32         ` Chee, Tien Fong
2019-03-06  4:52   ` Dinh Nguyen
2019-03-07  8:24     ` Chee, Tien Fong
2019-03-07 15:33       ` Dinh Nguyen
2019-03-08  4:36         ` Chee, Tien Fong

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