From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chee, Tien Fong <tien.fong.chee@intel.com>
Date: Fri, 8 Mar 2019 03:43:33 +0000
Subject: [U-Boot] [PATCH 1/4] ARM: socfpga: Disable D cache in SPL
In-Reply-To: <20190306210534.9365-1-marex@denx.de>
References: <20190306210534.9365-1-marex@denx.de>
Message-ID: <1552016612.9843.2.camel@intel.com>
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To: u-boot@lists.denx.de

On Wed, 2019-03-06 at 22:05 +0100, Marek Vasut wrote:
> The bootrom seems to leave the D-cache in messed up state, make sure
> the SPL disables it so it can not interfere with operation.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Chin Liang See <chin.liang.see@intel.com>
> Cc: Dinh Nguyen <dinguyen@kernel.org>
> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
> Cc: Tien Fong Chee <tien.fong.chee@intel.com>

Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>

> ---
>  arch/arm/mach-socfpga/spl_a10.c         | 2 ++
>  include/configs/socfpga_arria10_socdk.h | 2 --
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-
> socfpga/spl_a10.c
> index c97eacb424..c8e73d47c0 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -77,6 +77,8 @@ void spl_board_init(void)
>  
>  void board_init_f(ulong dummy)
>  {
> +	dcache_disable();
> +
>  	socfpga_init_security_policies();
>  	socfpga_sdram_remap_zero();
>  
> diff --git a/include/configs/socfpga_arria10_socdk.h
> b/include/configs/socfpga_arria10_socdk.h
> index 58e446b60a..0f116fbf2d 100644
> --- a/include/configs/socfpga_arria10_socdk.h
> +++ b/include/configs/socfpga_arria10_socdk.h
> @@ -15,8 +15,6 @@
>  /*
>   * U-Boot general configurations
>   */
> -/* Cache options */
> -#define CONFIG_SYS_DCACHE_OFF
>  
>  /* Memory configurations  */
>  #define PHYS_SDRAM_1_SIZE		0x40000000