[U-Boot] [PATCH 03/10] ddr: altera: s10: Add multiple memory banks support

[Ley Foon Tan <ley.foon.tan@intel.com>]

On Tue, 2019-03-12 at 14:05 +0000, Westergreen, Dalon wrote:
> On Tue, 2019-03-12 at 11:44 +0100, Marek Vasut wrote:
> > 
> > On 3/12/19 9:31 AM, Ley Foon Tan wrote:
> > > 
> > > Setup bank start address and size based on total SDRAM
> > > memory size calculated from hardware. Update sdram_size_check()
> > > to support multiple banks.
> > > 
> > > Stratix10 supports up to 2 memory banks.
> > > 
> > > Bank 0: Address 0, size 2GB
> > > Bank 1: Address 0x100000000, size 124GB
> > > 
> > > Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com>
> > > Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
> > Shouldn't Quartus generate some sort of DT which gives you all the
> > DRAM
> > layout information ? Then you won't need any of this
> > CONFIG_NR_DRAM_BANKS stuff, but you would be able to extract such
> > info
> > from DT and apply the sanity check only on DRAM you know exists.
> > 
> Yes, I think this can be much cleaner and the dts should provide the
> bank
> information rather than creating the banks from the determined dram
> size.
> 
> The determined dram size can just be a check to validate the bank
> configuration
> in the dts.

Okay.Then user needs update memory node in dts for different SDRAM
size.

Regards
Ley Foon
> 
> so
> 
> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
> b/arch/arm/dts/socfpga_stratix10_socdk.dts
> index 6e8ddcd9f4..94c71bb0ed 100644
> --- a/arch/arm/dts/socfpga_stratix10_socdk.dts
> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts
> @@ -36,7 +36,9 @@
> 
>         memory {
>                 device_type = "memory";
> -               reg = <0 0 0 0x80000000>; /* 2GB */
> +               /* 4GB */
> +               reg = < 0 0x00000000 0 0x80000000
> +                       1 0x80000000 0 0x80000000>;
>                 u-boot,dm-pre-reloc;
>         };
>  };
> 
> --dalon
> 
> 
>