From mboxrd@z Thu Jan  1 00:00:00 1970
From: Chee, Tien Fong <tien.fong.chee@intel.com>
Date: Mon, 15 Apr 2019 03:52:16 +0000
Subject: [U-Boot] [PATCH v12 0/9] Add support for loading FPGA bitstream
In-Reply-To: <20190319085019.6647-1-tien.fong.chee@intel.com>
References: <20190319085019.6647-1-tien.fong.chee@intel.com>
Message-ID: <1555300335.10873.0.camel@intel.com>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 8bit
To: u-boot@lists.denx.de

On Tue, 2019-03-19 at 16:50 +0800, tien.fong.chee at intel.com wrote:
> From: Tien Fong Chee <tien.fong.chee@intel.com>
> 
> This version mainly resolved comments from Dinh in [v11].
> 
> This series is working on top of u-boot.git http://git.denx.de/u-boot
> .git
> 
> These patches are required before applying this series of patches
> 1. [U-Boot,v4] misc: fs_loader: Add support for initializing block
> device
> https://patchwork.ozlabs.org/project/uboot/list/?series=89282 (done
> review)
> 
> 2. [U-Boot] fpga: Replace char * with const char * for filename
> https://patchwork.ozlabs.org/patch/1042665/ (done review)
> 
> 3. [U-Boot] misc: fs_loader: Replace label with DT phandle
> https://patchwork.ozlabs.org/patch/1051782/ (under review)
> 
> [v11]: https://www.mail-archive.com/u-boot at lists.denx.de/msg318174.ht
> ml
> [v10]: https://www.mail-archive.com/u-boot at lists.denx.de/msg318167.ht
> ml
> [v9]: https://www.mail-archive.com/u-boot at lists.denx.de/msg316086.htm
> l
> [v8]: https://www.mail-archive.com/u-boot at lists.denx.de/msg316086.htm
> l
> [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.htm
> l
> 
> Tien Fong Chee (9):
>   ARM: socfpga: Description on FPGA bitstream type and file name for
>     Arria 10
>   ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
>   ARM: socfpga: Cleaning up and ensuring consistent format messages
> in
>     driver
>   ARM: socfpga: Moving the watchdog reset to the for-loop status
> polling
>   ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
>   ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
>   spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
>   ARM: socfpga: Synchronize the configuration for A10 SoCDK
>   ARM: socfpga: Increase Malloc pool size to support FAT filesystem
> in
>     SPL
> 
>  arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts       |  17 +
>  .../include/mach/fpga_manager_arria10.h            |  40 +-
>  arch/arm/mach-socfpga/spl_a10.c                    |  31 +-
>  board/altera/arria10-socdk/fit_spl_fpga.its        |  38 ++
>  configs/socfpga_arria10_defconfig                  |  22 +-
>  .../fpga/altera-socfpga-a10-fpga-mgr.txt           |  26 +-
>  drivers/fpga/socfpga_arria10.c                     | 514
> ++++++++++++++++++++-
>  include/configs/socfpga_common.h                   |   4 +-
>  include/image.h                                    |   4 +
>  9 files changed, 664 insertions(+), 32 deletions(-)
>  create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
> 
Any comment about this series of patches?

Thanks.

Regards,
TF.