[U-Boot] [PATCH v12 9/9] ARM: socfpga: Increase Malloc pool size to support FAT filesystem in SPL

[Chee, Tien Fong <tien.fong.chee@intel.com>]

On Sat, 2019-04-27 at 21:50 +0200, Simon Goldschmidt wrote:
> 
> On 19.03.19 09:50, tien.fong.chee at intel.com wrote:
> > 
> > From: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > Increasing Malloc pool size up to 0x15000 is required to support
> > FAT in SPL
> > . The result of calculation is come from after applying some few
> > patches
> "Some few patches"? What should that mean? Either you refer to the 
> current state or you can refer to the patchwork items.
> 
> > 
> > which are required for optimizing vfat and maximizing resusable of
> > the
> > memory pool, and then followed by the size required come from
> > default max
> > cluster(0x10000) + others(0x2000) + additional memory for
> > headroom(0x3000).
> > Previous records of describing these few patches can be checked
> > from here
> > [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg314511.h
> > tml .
> Why do you refer to mail-archive.com instead of patchwork?
Contains the cover letter in case reviewer need to know more
information.

Thanks.
> 
> > 
> > 
> > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
> > 
> > ---
> > 
> > changes for v12
> > - Improved the commit messages.
> > 
> > changes for v11
> > - No changes.
> > 
> > changes for v10
> > - No changes.
> > 
> > changes for v9
> > - No changes.
> > 
> > changes for v8
> > - Moved the FIT related configs to the patch of configuration for
> > FPGA
> >    SoCFPGA A10 SoCDK.
> > 
> > changes for v7
> > - Keep minimal configs.
> > ---
> >   include/configs/socfpga_common.h | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/include/configs/socfpga_common.h
> > b/include/configs/socfpga_common.h
> > index 181af9b646..22533036ed 100644
> > --- a/include/configs/socfpga_common.h
> > +++ b/include/configs/socfpga_common.h
> > @@ -1,6 +1,6 @@
> >   /* SPDX-License-Identifier: GPL-2.0+ */
> >   /*
> > - * Copyright (C) 2012 Altera Corporation <www.altera.com>
> > + * Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
> >    */
> >   #ifndef __CONFIG_SOCFPGA_COMMON_H__
> >   #define __CONFIG_SOCFPGA_COMMON_H__
> > @@ -254,7 +254,7 @@ unsigned int
> > cm_get_qspi_controller_clk_hz(void);
> >   #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> >   /* SPL memory allocation configuration, this is for FAT
> > implementation */
> >   #ifndef CONFIG_SYS_SPL_MALLOC_START
> > -#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
> > +#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00015000
> >   #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_S
> > IZE - \
> >   					 CONFIG_SYS_SPL_MALLOC_SI
> > ZE + \
> >   					 CONFIG_SYS_INIT_RAM_ADDR
> > )
> >