[U-Boot] [PATCH v1 1/3] ARM: socfpga: stratix10: Add HPS execution stage notification function

[chee.hong.ang at intel.com <chee.hong.ang@intel.com>]

From: "Ang, Chee Hong" <chee.hong.ang@intel.com>

Add a new mailbox command "HPS_STAGE_NOTIFY" to notify Secure Device
Manager (SDM) on the stage of HPS code execution. In general, there
are three main code execution stages: First Stage Boot Loader (FSBL)
which is U-Boot SPL, Second Stage Boot Loader (SSBL) which is U-Boot,
and the Operating System which is Linux.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Ang, Chee Hong <chee.hong.ang@intel.com>
---
 arch/arm/mach-socfpga/include/mach/mailbox_s10.h | 7 +++++++
 arch/arm/mach-socfpga/mailbox_s10.c              | 6 ++++++
 2 files changed, 13 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index ae728a5..e815bdf 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -87,6 +87,12 @@ enum ALT_SDM_MBOX_RESP_CODE {
 #define MBOX_QSPI_CLOSE		51
 #define MBOX_QSPI_DIRECT	59
 #define MBOX_REBOOT_HPS		71
+#define MBOX_HPS_STAGE_NOTIFY	93
+
+/* Defines for HPS_STAGE_NOTIFY */
+#define HPS_EXECUTION_STATE_FSBL	0
+#define HPS_EXECUTION_STATE_SSBL	1
+#define HPS_EXECUTION_STATE_OS		2
 
 /* Mailbox registers */
 #define MBOX_CIN			0	/* command valid offset */
@@ -146,6 +152,7 @@ int mbox_qspi_open(void);
 #endif
 
 int mbox_reset_cold(void);
+int mbox_hps_stage_notify(u32 execution_stage);
 int mbox_get_fpga_config_status(u32 cmd);
 int mbox_get_fpga_config_status_psci(u32 cmd);
 #endif /* _MAILBOX_S10_H_ */
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c
index 4498ab5..250df84 100644
--- a/arch/arm/mach-socfpga/mailbox_s10.c
+++ b/arch/arm/mach-socfpga/mailbox_s10.c
@@ -390,6 +390,12 @@ int __secure mbox_get_fpga_config_status_psci(u32 cmd)
 	return mbox_get_fpga_config_status_common(cmd);
 }
 
+int mbox_hps_stage_notify(u32 execution_stage)
+{
+	return mbox_send_cmd(MBOX_ID_UBOOT, MBOX_HPS_STAGE_NOTIFY,
+			     MBOX_CMD_DIRECT, 1, &execution_stage, 0, 0, NULL);
+}
+
 int mbox_send_cmd(u8 id, u32 cmd, u8 is_indirect, u32 len, u32 *arg,
 		  u8 urgent, u32 *resp_buf_len, u32 *resp_buf)
 {
-- 
2.7.4